CAT93C56LI-G CATALYST SEMICONDUCTOR, CAT93C56LI-G Datasheet
CAT93C56LI-G
Specifications of CAT93C56LI-G
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CAT93C56LI-G Summary of contents
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CAT93C56, CAT93C57 2-Kb Microwire Serial CMOS EEPROM Description The CAT93C56/ 2−kb CMOS Serial EEPROM device which is organized as either 128 registers of 16 bits (ORG pin at V registers of 8 bits (ORG pin at GND). Each ...
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Table 1. ABSOLUTE MAXIMUM RATINGS Parameters Storage Temperature Voltage on Any Pin with Respect to Ground (Note 1) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is ...
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Table 4. D.C. OPERATING CHARACTERISTICS, CAT93C56/57, Die Rev. E – Mature Product (CAT93C56, Rev. E – NOT RECOMMENDED FOR NEW DESIGNS) Symbol Parameter I Power Supply Current (Write) CC1 I Power Supply Current (Read) CC2 I Power Supply Current (Standby) ...
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Table 6. A.C. CHARACTERISTICS (V = +1.8V to +5.5V −40°C to +125°C, unless otherwise specified Symbol t CS Setup Time CSS t CS Hold Time CSH t DI Setup Time DIS t DI Hold Time DIH ...
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Table 9. A.C. TEST CONDITIONS Input Rise and Fall Times Input Pulse Voltages Timing Reference Voltages Input Pulse Voltages Timing Reference Voltages Output Load Device Operation The CAT93C56/ 2048−bit nonvolatile memory intended for use with industry standard microprocessors. ...
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The format for all instructions sent to the device is a logical “1” start bit, a 2−bit (or 4−bit) opcode, 7−bit address (CAT93C57) / 8−bit address (CAT93C56) (an additional bit Table 10. INSTRUCTION SET Start Bit Instruction Device Type READ ...
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Read Upon receiving a READ command and an address (clocked into the DI pin), the DO pin of the CAT93C56/57 will come out of the high impedance state and, after sending an initial dummy zero bit, will begin shifting out ...
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Write After receiving a WRITE command (Figure 5), address and the data, the CS (Chip Select) pin must be deselected for a minimum The falling edge of CS will start the CSMIN self clocking clear and data ...
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Erase All Upon receiving an ERAL command (Figure 7), the CS (Chip Select) pin must be deselected for a minimum The falling edge of CS will start the self clocking CSMIN clear cycle of all memory locations ...
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PIN # 1 IDENTIFICATION D TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MS-001. PACKAGE DIMENSIONS PDIP−8, 300 mils CASE 646AA−01 ISSUE A SYMBOL ...
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PIN # 1 IDENTIFICATION TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. PACKAGE DIMENSIONS SOIC 8, 150 mils CASE 751BD−01 ISSUE O SYMBOL ...
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PIN#1 IDENTIFICATION TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with EIAJ EDR-7320. PACKAGE DIMENSIONS SOIC−8, 208 mils CASE 751BE−01 ISSUE O SYMBOL ...
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E1 e TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. PACKAGE DIMENSIONS TSSOP8, 4.4x3 CASE 948AL−01 ISSUE O SYMBOL MIN A A1 0.05 A2 ...
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D E PIN#1 INDEX AREA TOP VIEW SYMBOL MIN NOM A 0.70 0.75 A1 0.00 0.02 A2 0.45 0.55 A3 0.20 REF b 0.20 0.25 D 1.90 2.00 D2 1.30 1.40 E 2.90 3.00 E2 1.20 1.30 e 0.50 TYP ...
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D PIN#1 INDEX AREA TOP VIEW SYMBOL MIN NOM A 0.70 0.75 A1 0.00 0.02 A3 0.20 REF b 0.23 0.30 D 2.90 3.00 D2 2.20 −−− E 2.90 3.00 E2 1.40 −−− e 0.65 TYP L 0.20 0.30 Notes: ...
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Example of Ordering Information CAT93C56, Die Rev. G, New Product Prefix Device # Suffix CAT 93C56 V Company ID Product Number 93C56 Package L: PDIP V: SOIC, JEDEC X: SOIC, EIAJ (Note 14) Y: TSSOP VP2: TDFN ( ...
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ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for ...