M24LR64-RMN6/2 STMicroelectronics, M24LR64-RMN6/2 Datasheet - Page 37

• Manufacturer Part Number: M24LR64-RMN6/2
• Description: EEPROM, 64K, DUAL INTERFACE, 8SOIC
• Manufacturer: STMicroelectronics

Specifications of M24LR64-RMN6/2

• Memory Size: 64Kbit
• Clock Frequency: 400kHz
• Access Time: 900ns
• Supply Voltage Range: 1.8V To 5V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC
• Memory Configuration: 8192 X 8, 2048 X 32
• Interface Type: I2C, Serial, 2-Wire
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

M24LR64-R
6
7
User memory initial state
The device is delivered with all bits in the user memory array set to 1 (each byte contains
FFh).
RF device operation
The M24LR64-R is divided into 64 sectors of 32 blocks of 32 bits as shown in
sector can be individually read- and/or write-protected using a specific lock or password
command.
Read and Write operations are possible if the addressed block is not protected. During a
Write, the 32 bits of the block are replaced by the new 32-bit value.
The M24LR64-R also has a 64-bit block that is used to store the 64-bit unique identifier
(UID). The UID is compliant with the ISO 15963 description, and its value is used during the
anticollision sequence (Inventory). This block is not accessible by the user and its value is
written by ST on the production line.
The M24LR64-R also includes an AFI register in which the application family identifier is
stored, and a DSFID register in which the data storage family identifier used in the
anticollision algorithm is stored. The M24LR64-R has three additional 32-bit blocks in which
the password codes are stored.
Doc ID 15170 Rev 11
User memory initial state
Table
5. Each
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