S25FL128P0XNFI001 Spansion Inc., S25FL128P0XNFI001 Datasheet - Page 32

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S25FL128P0XNFI001

Manufacturer Part Number
S25FL128P0XNFI001
Description
IC, FLASH, 128MBIT, 104MHZ, WSON-8
Manufacturer
Spansion Inc.
Datasheet

Specifications of S25FL128P0XNFI001

Memory Type
Flash
Memory Size
128Mbit
Ic Interface Type
Serial, SPI
Clock Frequency
104MHz
Supply Voltage Range
2.7 To 3.6 V
Memory Case Style
WSON
No. Of Pins
8
Cell Type
NOR
Density
128Mb
Access Time (max)
20ns
Interface Type
Parallel/Serial-SPI
Boot Type
Not Required
Address Bus
1b
Operating Supply Voltage (typ)
3/3.3V
Operating Temp Range
-40C to 85C
Package Type
WSON
Program/erase Volt (typ)
2.7 to 3.6V
Sync/async
Async/Sync
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
1b
Number Of Words
128M
Supply Current
22mA
Mounting
Surface Mount
Pin Count
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
S25FL128P0XNFI001
Manufacturer:
SPANSION
Quantity:
300
Part Number:
S25FL128P0XNFI001
Manufacturer:
VISION
Quantity:
2 300
32
11.9.2
Parallel Mode
In parallel mode, the maximum SCK clock frequency is 10 MHz. The device requires a single clock cycle
instead of eight clock cycles to access the next data byte. The memory content input method is the same as
serial mode. The only difference is that a byte of data is input per clock cycle instead of a single bit. This
means that 256 bytes of data can be copied into the 256 byte wide page write buffer in 256 clock cycles
instead of in 2,048 clock cycles.
Notes
1. 1st Byte = “02h”.
2. 2nd Byte = Address 1, MSB first (bits 23 through 16).
3. 3rd Byte = Address 2, MSB first (bits 15 through 8).
4. 4th Byte = Address 3, MSB first (bits 7 through 0).
5. 5th Byte = first write data byte.
6. In parallel mode, the fastest access clock frequency (Fsck) is 10 MHz (SCK pin clock frequency).
7. Programming in parallel mode requires an “Parallel mode Entry” command (55h) before the program command. Once in the parallel
PO[7-0]
mode, the flash memory will not exit parallel mode until an “Exit Parallel Mode” (45h) command is given to the flash device, or upon power
down / power up sequence completion.
SCK
CS#
SI
0
1
Figure 11.15 Parallel Page Program (PP) Instruction Sequence
2
High-Z
Instruction (02h)
3
90h
4
5
6
S25FL128P
7
MSB
23 22 21
8
D a t a
9
Address Byte 1
10 11 12 13 14 15
20 19 18
S h e e t
17
16
15
16
Address
Byte 2
S25FL128P_00_08 September 8, 2009
8
23 24
7
Address
Byte 3
0
31
Byte
1
32 33
Byte
2
Byte
n
n
Hi-Z

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