S29AL032D70TFI030 Spansion Inc., S29AL032D70TFI030 Datasheet - Page 36
![IC, FLASH, 32MBIT, 70NS, TSOP-48](/photos/19/5/190512/4243308_sml.jpg)
S29AL032D70TFI030
Manufacturer Part Number
S29AL032D70TFI030
Description
IC, FLASH, 32MBIT, 70NS, TSOP-48
Manufacturer
Spansion Inc.
Datasheet
1.S29AL032D70TFI000.pdf
(67 pages)
Specifications of S29AL032D70TFI030
Memory Type
Flash
Memory Size
32Mbit
Memory Configuration
4M X 8 / 2M X 16
Ic Interface Type
CFI, Parallel
Access Time
70ns
Supply Voltage Range
2.7V To 3.6V
Memory Case Style
TSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S29AL032D70TFI030
Manufacturer:
SPANSION
Quantity:
2 526
Company:
Part Number:
S29AL032D70TFI030
Manufacturer:
TOSHIBA
Quantity:
2 437
Part Number:
S29AL032D70TFI030
Manufacturer:
SPANSION
Quantity:
20 000
11.7
34
Chip Erase Command Sequence
Note
See
Chip erase is a six bus-cycle operation. The chip erase command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical erase. The system is not required to provide any
controls or timings during these operations.
for the chip erase command sequence.
Any commands written to the chip during the Embedded Erase algorithm are ignored. Note that a hardware
reset during the chip erase operation immediately terminates the operation. The Chip Erase command
sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity.
The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. See
Operation Status on page 40
complete, the device returns to reading array data and addresses are no longer latched.
Figure 11.2 on page 36
page 52
Table 11.2
for parameters, and to
for program command sequence.
illustrates the algorithm for the erase operation. See
for information on these status bits. When the Embedded Erase algorithm is
Increment Address
Figure 17.6 on page 53
Figure 11.1 Program Operation
S29AL032D
Table 11.2 on page 38
in progress
Embedded
D a t a
algorithm
Program
S h e e t
for timing diagrams.
No
Command Sequence
Write Program
Last Address?
Programming
from System
Verify Data?
Completed
shows the address and data requirements
Data Poll
START
Yes
Yes
Erase/Program Operations on
S29AL032D_00_A9 January 19, 2007
No
Write