AM29F040B-90JI Spansion Inc., AM29F040B-90JI Datasheet - Page 4

• Manufacturer Part Number: AM29F040B-90JI
• Description: IC, FLASH, 4MBIT, 90NS, LCC-32
• Manufacturer: Spansion Inc.

Specifications of AM29F040B-90JI

• Memory Type: Flash
• Memory Size: 4Mbit
• Memory Configuration: 512K X 8
• Access Time: 90ns
• Supply Voltage Range: 4.5V To 5.5V
• Memory Case Style: PLCC
• No. Of Pins: 32
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

GENERAL DESCRIPTION
The Am29F040B is a 4 Mbit, 5.0 volt-only Flash mem-
ory organized as 524,288 Kbytes of 8 bits each. The
512 Kbytes of data are divided into eight sectors of 64
Kbytes each for flexible erase capability. The 8 bits of
data appear on DQ0–DQ7. The Am29F040B is offered
in 32-pin PLCC or TSOP packages. This device is de-
signed to be programmed in-system with the standard
system 5.0 volt V
quired for write or erase operations. The device can also
be programmed in standard EPROM programmers.
This device is manufactured using AMD’s 0.32 µm pro-
cess technology, and offers all the features and
benefits of the Am29F040, which was manufactured
using 0.5 µm process technology. In addtion, the
Am29F040B has a second toggle bit, DQ2, and also of-
fers the ability to program in the Erase Suspend mode.
The standard Am29F040B offers access times of 55,
70 and 90 ns, allowing high-speed microprocessors to
operate without wait states. To eliminate bus contention
the device has separate chip enable (CE#), write en-
able (WE#) and output enable (OE#) controls.
The device requires only a single 5.0 volt power sup-
ply for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write cy-
cles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto-
2
CC
supply. A 12.0 volt V
PP
D A T A
is not re-
Am29F040B
S H E E T
matically times the program pulse widths and verifies
proper cell margin.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by reading the DQ7 (Data#
Polling) and DQ6 (toggle) status bits. After a program
or erase cycle has been completed, the device is ready
to read array data or accept another command.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
V
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved via programming equipment.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The system can place the device into the standby mode.
Power consumption is greatly reduced in this mode.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunneling.
The data is programmed using hot electron injection.
CC
detector that automatically inhibits write opera-
21445E8 November 11, 2009