PIC16F1827-I/SS Microchip Technology, PIC16F1827-I/SS Datasheet - Page 112
![IC, 8BIT MCU, PIC16F, 32MHZ, SSOP-20](/photos/6/81/68119/150-28-ssop_sml.jpg)
PIC16F1827-I/SS
Manufacturer Part Number
PIC16F1827-I/SS
Description
IC, 8BIT MCU, PIC16F, 32MHZ, SSOP-20
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheets
1.PIC16F722-ISS.pdf
(8 pages)
2.PIC16F1826-IP.pdf
(406 pages)
3.PIC16F1826-IP.pdf
(12 pages)
4.PIC16F1826-IP.pdf
(8 pages)
5.PIC16F1826-IP.pdf
(40 pages)
6.PIC16LF1827-ISS.pdf
(400 pages)
Specifications of PIC16F1827-I/SS
Controller Family/series
PIC16F
Eeprom Memory Size
256Byte
Ram Memory Size
384Byte
Cpu Speed
32MHz
No. Of Timers
5
Interface
EUSART, I2C, SPI
Core Size
8 Bit
Program Memory Size
4kWords
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SSOP
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
384 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
15
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F1827-I/SS
Manufacturer:
NELL
Quantity:
45
- PIC16F722-ISS PDF datasheet
- PIC16F1826-IP PDF datasheet #2
- PIC16F1826-IP PDF datasheet #3
- PIC16F1826-IP PDF datasheet #4
- PIC16F1826-IP PDF datasheet #5
- PIC16LF1827-ISS PDF datasheet #6
- Current page: 112 of 406
- Download datasheet (4Mb)
PIC16F/LF1826/27
11.3.2
While executing code, program memory can only be
erased by rows. To erase a row:
1.
2.
3.
4.
5.
6.
See Example 11-4.
After the “BSF EECON1,WR” instruction, the processor
requires two cycles to set up the erase operation. The
user must place two NOP instructions after the WR bit is
set. The processor will halt internal operations for the
typical 2 ms erase time. This is not Sleep mode as the
clocks and peripherals will continue to run. After the
erase cycle, the processor will resume operation with
the third instruction after the EECON1 write instruction.
11.3.3
Program memory is programmed using the following
steps:
1.
2.
3.
4.
Before writing to program memory, the word(s) to be
written must be erased or previously unwritten. Pro-
gram memory can only be erased one row at a time. No
automatic erase occurs upon the initiation of the write.
Program memory can be written one or more words at
a time. The maximum number of words written at one
time is equal to the number of write latches. See
Figure 11-2 (block writes to program memory with 32
write latches) for more details. The write latches are
aligned to the address boundary defined by EEADRL
as shown in Table 11-1. Write operations do not cross
these boundaries. At the completion of a program
memory write operation, the write latches are reset to
contain 0x3FFF.
DS41391C-page 112
Load the EEADRH:EEADRL register pair with
the address of new row to be erased.
Clear the CFGS bit of the EECON1 register.
Set the EEPGD, FREE, and WREN bits of the
EECON1 register.
Write 55h, then AAh, to EECON2 (Flash
programming unlock sequence).
Set control bit WR of the EECON1 register to
begin the erase operation.
Poll the FREE bit in the EECON1 register to
determine when the row erase has completed.
Load the starting address of the word(s) to be
programmed.
Load the write latches with data.
Initiate a programming operation.
Repeat steps 1 through 3 until all data is written.
ERASING FLASH PROGRAM
MEMORY
WRITING TO FLASH PROGRAM
MEMORY
Preliminary
The following steps should be completed to load the
write latches and program a block of program memory.
These steps are divided into two parts. First, all write
latches are loaded with data except for the last program
memory location. Then, the last write latch is loaded
and the programming sequence is initiated. A special
unlock sequence is required to load a write latch with
data or initiate a Flash programming operation. This
unlock sequence should not be interrupted.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Load the EEDATH:EEDATL register pair with
11. Write 55h, then AAh, to EECON2, then set the
It is not necessary to load the entire write latch block
with user program data. However, the entire write latch
block will be written to program memory.
An example of the complete write sequence for eight
words is shown in Example 11-5. The initial address is
loaded into the EEADRH:EEADRL register pair; the
eight words of data are loaded using indirect addressing.
Note:
Set the EEPGD and WREN bits of the EECON1
register.
Clear the CFGS bit of the EECON1 register.
Set the LWLO bit of the EECON1 register. When
the LWLO bit of the EECON1 register is ‘1’, the
write sequence will only load the write latches
and will not initiate the write to Flash program
memory.
Load the EEADRH:EEADRL register pair with
the address of the location to be written.
Load the EEDATH:EEDATL register pair with
the program memory data to be written.
Write 55h, then AAh, to EECON2, then set the
WR bit of the EECON1 register (Flash
programming unlock sequence). The write latch
is now loaded.
Increment the EEADRH:EEADRL register pair
to point to the next location.
Repeat steps 5 through 7 until all but the last
write latch has been loaded.
Clear the LWLO bit of the EECON1 register.
When the LWLO bit of the EECON1 register is
‘0’, the write sequence will initiate the write to
Flash program memory.
the program memory data to be written.
WR bit of the EECON1 register (Flash
programming unlock sequence). The entire
latch block is now written to Flash program
memory.
If the number of write latches is smaller
than the erase block size, the code
sequence provided in Example 11-5 must
be repeated multiple times to fully program
an erased program memory row.
2010 Microchip Technology Inc.
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