PIC24FJ64GB004-I/ML Microchip Technology, PIC24FJ64GB004-I/ML Datasheet - Page 15

• Manufacturer Part Number: PIC24FJ64GB004-I/ML
• Description: IC, 16BIT MCU, PIC24F, 32MHZ, QFN-44
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24FJ64GB004-I/ML

• Controller Family/series: PIC24
• Ram Memory Size: 8KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Interface: I2C, LIN, SPI, UART, USB
• No. Of Pwm Channels: 5
• Core Size: 16 Bit
• Program Memory Size: 64 KB
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Embedded Interface Type: I2C, LIN, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

TABLE 1-2:
 2010 Microchip Technology Inc.
INT0
MCLR
OSCI
OSCO
PGEC1
PGED1
PGEC2
PGED2
PGEC3
PGED3
PMA0
PMA1
PMA2
PMA3
PMA4
PMA5
PMA6
PMA7
PMA8
PMA9
PMA10
PMCS1
PMBE
PMD0
PMD1
PMD2
PMD3
PMD4
PMD5
PMD6
PMD7
PMRD
PMWR
Legend:
Function
TTL = TTL input buffer
ANA = Analog level input/output
SOIC/SSOP
SPDIP/
28-Pin
16
10
22
21
10
12
18
17
16
24
—
—
—
—
—
—
—
—
—
11
PIC24FJ64GB004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
1
9
5
4
3
2
9
4
5
6
3
2
7
Pin Number
28-Pin
QFN
13
28
27
21
26
19
18
28
27
—
—
—
—
—
—
—
—
—
15
14
13
6
7
2
1
7
9
6
8
1
2
3
4
QFN/TQFP
44-Pin
43
18
30
31
22
21
20
19
27
38
37
13
32
35
12
30
36
21
22
23
44
43
20
19
11
24
9
8
3
2
4
5
1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
PIC24FJ64GB004 FAMILY
ST/TTL Parallel Master Port Chip Select 1 Strobe/Address Bit 15.
ST/TTL Parallel Master Port Data (Demultiplexed Master mode) or
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
Buffer
Input
ANA
ANA
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
—
—
—
—
—
—
—
—
—
—
—
—
ST = Schmitt Trigger input buffer
I
2
C™ = I
External Interrupt Input.
Master Clear (device Reset) Input. This line is brought low to
cause a Reset.
Main Oscillator Input Connection.
Main Oscillator Output Connection.
In-Circuit Debugger/Emulator/ICSP™ Programming Clock.
In-Circuit Debugger/Emulator/ICSP Programming Data.
In-Circuit Debugger/Emulator/ICSP Programming Clock.
In-Circuit Debugger/Emulator/ICSP Programming Data.
In-Circuit Debugger/Emulator/ICSP Programming Clock.
In-Circuit Debugger/Emulator/ICSP Programming Data.
Parallel Master Port Address Bit 0 Input (Buffered Slave
modes) and Output (Master modes).
Parallel Master Port Address Bit 1 Input (Buffered Slave
modes) and Output (Master modes).
Parallel Master Port Address (Demultiplexed Master modes).
Parallel Master Port Byte Enable Strobe.
Address/Data (Multiplexed Master modes).
Parallel Master Port Read Strobe.
Parallel Master Port Write Strobe.
2
C/SMBus input buffer
Description
DS39940D-page 15