PIC12LF1822-I/MF Microchip Technology, PIC12LF1822-I/MF Datasheet - Page 236
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PIC12LF1822-I/MF
Manufacturer Part Number
PIC12LF1822-I/MF
Description
IC, 8BIT MCU, PIC12, 32MHZ, DFN-8
Manufacturer
Microchip Technology
Series
PIC® XLP™ 12Fr
Datasheets
1.PIC12F1822T-ISN.pdf
(404 pages)
2.PIC12F1822T-ISN.pdf
(10 pages)
3.PIC12F1822-IMF.pdf
(398 pages)
Specifications of PIC12LF1822-I/MF
Controller Family/series
PIC12
No. Of I/o's
6
Eeprom Memory Size
256Byte
Ram Memory Size
128Byte
Cpu Speed
32MHz
No. Of Timers
3
Core Size
8 Bit
Program Memory Size
3.5KB
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DFN
Processor Series
PIC12LF
Core
PIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC12LF1822-I/MF
Manufacturer:
MICROCHIP
Quantity:
3 600
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PIC12F/LF1822/PIC16F/LF1823
25.2.2
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSP1CON1<5:0> and SSP1STAT<7:6>).
These control bits allow the following to be specified:
• Master mode (SCK1 is the clock output)
• Slave mode (SCK1 is the clock input)
• Clock Polarity (Idle state of SCK1)
• Data Input Sample Phase (middle or end of data
• Clock Edge (output data on rising/falling edge of
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
To enable the serial port, SSP1 Enable bit, SSP1EN of
the SSP1CON1 register must be set. To reset or recon-
figure SPI mode, clear the SSP1EN bit, re-initialize the
SSP1CONx registers and then set the SSP1EN bit.
This configures the SDI, SDO, SCK and SS pins as
serial port pins. For the pins to behave as the serial port
function, some must have their data direction bits (in
the TRIS register) appropriately programmed as
follows:
• SDI must have corresponding TRIS bit set
• SDO must have corresponding TRIS bit cleared
• SCK (Master mode) must have corresponding
• SCK (Slave mode) must have corresponding
• SS must have corresponding TRIS bit set
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
The MSSP1 consists of a transmit/receive shift register
(SSP1SR) and a buffer register (SSP1BUF). The
SSP1SR shifts the data in and out of the device, MSb
first. The SSP1BUF holds the data that was written to
the SSP1SR until the received data is ready. Once the
8 bits of data have been received, that byte is moved to
the SSP1BUF register. Then, the Buffer Full Detect bit,
BF of the SSP1STAT register, and the interrupt flag bit,
SSP1IF, are set. This double-buffering of the received
data (SSP1BUF) allows the next byte to start reception
before reading the data that was just received. Any
write
transmission/reception of data will be ignored and the
write collision detect bit, WCOL, of the SSP1CON1
register, will be set. User software must clear the
WCOL bit to allow the following write(s) to the
SSP1BUF register to complete successfully.
DS41413B-page 236
output time)
SCK1)
TRIS bit cleared
TRIS bit set
to
SPI MODE OPERATION
the
SSP1BUF
register
during
Preliminary
When the application software is expecting to receive
valid data, the SSP1BUF should be read before the
next byte of data to transfer is written to the SSP1BUF.
The Buffer Full bit, BF of the SSP1STAT register,
indicates when SSP1BUF has been loaded with the
received data (transmission is complete). When the
SSP1BUF is read, the BF bit is cleared. This data may
be irrelevant if the SPI is only a transmitter. Generally,
the MSSP1 interrupt is used to determine when the
transmission/reception has completed. If the interrupt
method is not going to be used, then software polling
can be done to ensure that a write collision does not
occur.
The SSP1SR is not directly readable or writable and
can only be accessed by addressing the SSP1BUF
register. Additionally, the SSP1STAT register indicates
the various Status conditions.
2010 Microchip Technology Inc.
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