PIC24HJ256GP210A-I/PF Microchip Technology, PIC24HJ256GP210A-I/PF Datasheet - Page 165

• Manufacturer Part Number: PIC24HJ256GP210A-I/PF
• Description: IC, 16BIT MCU, PIC24H, 40MIPS, TQFP-100
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ256GP210A-I/PF

• Controller Family/series: PIC24
• Ram Memory Size: 16KB
• Cpu Speed: 40MIPS
• No. Of Timers: 9
• Interface: I2C, LIN, SPI, UART
• No. Of Pwm Channels: 8
• Core Size: 16 Bit
• Program Memory Size: 256 KB
• Core Processor: PIC
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Embedded Interface Type: I2C, LIN, SPI, UART
• Rohs Compliant: Yes
• Processor Series: PIC24HJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 9
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 32 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

REGISTER 16-3:
 2009 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12-2
bit 1
bit 0
FRMEN
R/W-0
U-0
—
FRMEN: Framed SPIx Support bit
1 = Framed SPIx support enabled (SSx pin used as frame sync pulse input/output)
0 = Framed SPIx support disabled
SPIFSD: Frame Sync Pulse Direction Control bit
1 = Frame sync pulse input (slave)
0 = Frame sync pulse output (master)
FRMPOL: Frame Sync Pulse Polarity bit
1 = Frame sync pulse is active-high
0 = Frame sync pulse is active-low
Unimplemented: Read as ‘0’
FRMDLY: Frame Sync Pulse Edge Select bit
1 = Frame sync pulse coincides with first bit clock
0 = Frame sync pulse precedes first bit clock
Unimplemented: Read as ‘0’
This bit must not be set to ‘1’ by the user application
SPIFSD
R/W-0
U-0
—
SPIxCON2: SPIx CONTROL REGISTER 2
W = Writable bit
‘1’ = Bit is set
PIC24HJXXXGPX06A/X08A/X10A
FRMPOL
R/W-0
U-0
—
U-0
U-0
Preliminary
—
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
U-0
—
—
U-0
U-0
—
—
x = Bit is unknown
FRMDLY
R/W-0
U-0
—
DS70592B-page 165
U-0
U-0
—
—
bit 8
bit 0