PIC24FJ192GA106-I/MR Microchip Technology, PIC24FJ192GA106-I/MR Datasheet - Page 6

• Manufacturer Part Number: PIC24FJ192GA106-I/MR
• Description: IC, 16BIT MCU, PIC24F, 32MHZ, QFN-64
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ192GA106-I/MR

• Controller Family/series: PIC24
• No. Of I/o's: 53
• Ram Memory Size: 16KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Core Size: 16 Bit
• Program Memory Size: 192KB
• Peripherals: ADC, Comparator, PWM, RTC, Timer
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, PMP, SPI, UART/USART
• Number Of I /o: 53
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240011, DM240001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC24FJ256GA110 FAMILY
4. Module: Pin Diagrams
5. Module: Memory Organization
DS80385B-page 6
In the 64-pin device pin diagram on page 2, the
reference to SCK1 on pin 35 is deleted. The
correct complete designation for this pin is “RPI45/
INT0/CN72/RF6”.
The SCK1 function is available only through Periph-
eral Pin Select (PPS), and is not permanently
multiplexed to any one pin on this device.
In Table 3-5 of the device data sheet (Interrupt
Controller Register Map), bits 4 and 3 of INTCON2
are incorrectly shown as unimplemented. These
positions are actually implemented as INT4EP and
INT3EP, respectively.
An amended partial version of the table with the
correct footnote is shown in Table 3-5 (additions in
bold).
(SFR Space)
6. Module: Memory Organization
In Table 3-18 of the device data sheet (PORTG
Register Map), the footnote references on the Bit 1
and Bit 0 columns are incorrect. These bits, and
their corresponding I/O channels, are actually
available on 80-pin devices.
An amended version of the table with the correct
footnote is shown in Table 3-18 (additions and
changes in bold).
(SFR Space)
© 2009 Microchip Technology Inc.