PIC24FJ256GB106-I/MR Microchip Technology, PIC24FJ256GB106-I/MR Datasheet - Page 36
![IC, 16BIT MCU, PIC24F, 32MHZ, QFN-64](/photos/12/13/121325/c04-149_mr_sml.jpg)
PIC24FJ256GB106-I/MR
Manufacturer Part Number
PIC24FJ256GB106-I/MR
Description
IC, 16BIT MCU, PIC24F, 32MHZ, QFN-64
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Datasheets
1.PIC24FJ128GA106-IPT.pdf
(52 pages)
2.PIC24FJ64GB106-IPT.pdf
(16 pages)
3.PIC24FJ64GB106-IPT.pdf
(352 pages)
4.PIC24FJ192GB108-IPT.pdf
(328 pages)
Specifications of PIC24FJ256GB106-I/MR
Controller Family/series
PIC24
No. Of I/o's
51
Ram Memory Size
16KB
Cpu Speed
32MHz
No. Of Timers
5
Core Size
16 Bit
Program Memory Size
256KB
Peripherals
ADC, Comparator, PWM, RTC, Timer
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, SPI, UART/USART, USB OTG
Number Of I /o
51
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
52
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1004 - PIC24 BREAKOUT BOARD
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24FJ256GB106-I/MR
Manufacturer:
TI
Quantity:
1 292
PIC24FJXXXGA1/GB1
TABLE 5-1:
5.2.4
All commands supported by the programming executive
are described in Section 5.2.5 “SCHECK Command”
through Section 5.2.12 “QVER Command”.
5.2.5
DS39907A-page 36
Legend: TBD = To Be Determined
Note 1:
15
Opcode
Length
Opcode Mnemonic
Ah
Bh
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Opcode
Field
SCHECK
READC
READP
RESERVED
PROGC
PROGP
PROGW
RESERVED
RESERVED
RESERVED
QBLANK
QVER
12 11
One row of code memory consists of (64) 24-bit words. Refer to Table 2-2 for device-specific information.
COMMAND DESCRIPTIONS
SCHECK COMMAND
PROGRAMMING EXECUTIVE COMMAND SET
0h
1h
(16-bit words)
Length
N/A
N/A
N/A
N/A
Description
99
1
3
4
4
5
3
1
Length
Time-out
1 ms/row
1 ms
1 ms
5 ms
5 ms
5 ms
1 ms
TBD
N/A
N/A
N/A
N/A
0
Sanity check.
Read an 8-bit word from the specified Device ID register.
Read N 24-bit instruction words of code memory starting from
the specified address.
Write an 8-bit word to the specified Device ID registers.
Program one row of code memory at the specified address,
then verify.
Program one instruction word of code memory at the specified
address, then verify.
Query the programming executive software version.
This command is reserved. It will return a NACK.
This command is reserved. It will return a NACK.
This command is reserved. It will return a NACK.
This command is reserved. It will return a NACK.
Query if the code memory is blank.
The SCHECK command instructs the programming
executive to do nothing but generate a response. This
command is used as a “Sanity Check” to verify that the
programming executive is operational.
Expected Response (2 words):
(1)
Note:
1000h
0002h
This instruction is not required for
programming
development purposes only.
Description
© 2007 Microchip Technology Inc.
but
is
provided
for