PIC32MX795F512L-80I/BG Microchip Technology, PIC32MX795F512L-80I/BG Datasheet - Page 12
![IC, 32BIT MCU, PIC32, 80MHZ, BGA-100](/photos/12/13/121347/121-xbga_sml.jpg)
PIC32MX795F512L-80I/BG
Manufacturer Part Number
PIC32MX795F512L-80I/BG
Description
IC, 32BIT MCU, PIC32, 80MHZ, BGA-100
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheets
1.PIC32MX320F032H-40IPT.pdf
(66 pages)
2.PIC32MX575F256H-80IMR.pdf
(2 pages)
3.PIC32MX575F256H-80IMR.pdf
(254 pages)
4.PIC32MX575F256H-80IMR.pdf
(14 pages)
5.PIC32MX575F256H-80IPT.pdf
(240 pages)
Specifications of PIC32MX795F512L-80I/BG
Controller Family/series
PIC32
Ram Memory Size
128KB
Cpu Speed
80MHz
No. Of Timers
5
Interface
CAN, I2C, SPI, UART, USB
No. Of Pwm Channels
5
Core Size
32 Bit
Program Memory Size
512 KB
Core Processor
MIPS32® M4K™
Speed
80MHz
Connectivity
CAN, Ethernet, I²C, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Program Memory Type
FLASH
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
121-TFBGA
Embedded Interface Type
CAN, I2C, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
PIC32MX7xx
Core
MIPS
3rd Party Development Tools
52713-733, 52714-737
Development Tools By Supplier
PG164130, DV164035, DV244005
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX795F512L-80I/BG
Manufacturer:
Microchip
Quantity:
316
Company:
Part Number:
PIC32MX795F512L-80I/BG
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC32MX
6.3
Format:
Purpose:
Description (in sequence):
FIGURE 6-5:
FIGURE 6-6:
DS61145G-page 12
oData = XferData (iData)
To clock data to and from the register selected by the
command.
1.
2.
3.
4.
The TMS Header is clocked into the device to
select the Shift DR state.
The data is clocked in/out of the device on
TDI/TDO while holding signal TMS low.
The last MSb of the data is clocked in/out
while setting TMS high.
The TMS Footer is clocked in on TMS to return
the TAP controller to the Run/Test Idle state.
TMS
TCK
TDO
TDI
XferData Pseudo Operation
PGC
PGD
TDI = iLSb
TDI = 0
TDI = 0
‘1’
Data (31’h12) + TMS = 0
TMS Header = 100
XferData 4-WIRE
XferData 2-WIRE (4-PHASE)
TMS = 0
TMS = 1
TMS = 1
‘0’
TDO = oLSb+1
TDO =
TDO =
TMS Footer =
...
‘0’
X
X
TMS Header =
TDI = 0
oLSb
10
iLSb
TDI = 0
Data (32’h12)
TDI = iMSb
Data (MSb) + TMS Footer = 1
TMS = 0
TMS = 0
100
TMS = 1
Restrictions:
Example:
None.
oData = XferData (32’h12)
Data (MSb)
TDO =
+ TMS = 1
TDO =
oMSb
iMSb
‘1’
X
X
TDO =
TDI = 0
X
‘1’
TMS Footer = 10
© 2010 Microchip Technology Inc.
TMS = 0
‘0’
TDO = oLSb