ADL5320ARKZ Analog Devices Inc, ADL5320ARKZ Datasheet - Page 11

• Manufacturer Part Number: ADL5320ARKZ
• Description: AMP, DVR, RF, 400MHZ-2.7GHZ, 3SOT89
• Manufacturer: Analog Devices Inc

Specifications of ADL5320ARKZ

• Frequency Range: 400MHz To 2.7GHz
• Noise Figure Typ: 5.1dB
• Power Dissipation Pd: 520mW
• Supply Current: 104mA
• Supply Voltage Range: 4.5V To 5.5V
• Rf Ic Case: RoHS Compliant
• Gain: 17dB
• Rf Type: Broadband

BASIC LAYOUT CONNECTIONS
The basic connections for operating the ADL5320 are shown in
Figure 26.
Table 5 lists the required matching components. Capacitors C1,
C2, C3, C4, and C7 are Murata GRM155 series (0402 size) and
Inductor L1 is a Coilcraft 0603CS series (0603 size). For all
frequency bands, the placement of C3 and C7 are critical. From
2300 MHz to 2700 MHz, the placement of C2 is also important.
Table 6 lists the recommended component placement for
various frequencies.
A 5 V dc bias is supplied through L1 which is connected to
RF
supply decoupling capacitors are also required. The typical
current consumption for the ADL5320 is 110 mA.
Table 5. Recommended Components for Basic Connections
Frequency (MHz)
450 to 500
800 to 960
1805 to 1880
1930 to 1990
2110 to 2170
2300 to 2400
2500 to 2700
Table 6. Matching Component Spacing
Frequency (MHz)
450 to 500
800 to 960
1805 to 2170
2300 to 2400
2500 to 2700
RF
IN
1
2
OUT
SEE TABLE 5 FOR FREQUENCY SPECIFIC COMPONENTS.
SEE TABLE 10 FOR RECOMMENDED COMPONENT SPACING.
C1
(Pin 3). In addition to C4, 10 nF and 10 μF power
1
λ1
C3
2
1
1
Figure 26. Basic Connections
ADL5320
(2)
2
3
GND
λ2
2
VSUP
C4
L1
C6 10µF
C5 10nF
λ3
1
1
2
C1 (pF)
100
47
22
22
22
12
12
C7
λ4
1
2
C2
1
λ1 (mils)
391
200
300
225
142
RF
OUT
Rev. 0 | Page 11 of 16
C2 (pF)
100
47
22
22
22
2.2
1.0
SOLDERING INFORMATION AND RECOMMENDED
PCB LAND PATTERN
Figure 27 shows the recommended land pattern for the ADL5320.
To minimize thermal impedance, the exposed paddle on the
SOT-89 package underside is soldered down to a ground plane
along with Pin 2. If multiple ground layers exist, they should
be stitched together using vias. For more information on land
pattern design and layout, refer to the Application Note AN-772,
A Design and Manufacturing Guide for the Lead Frame Chip
Scale Package (LFCSP).
λ2 (mils)
75
75
75
75
75
C3 (pF)
18
6.8
0.5
0.5
0.5
1.2
1.8
5.56mm
Figure 27. Recommended Land Pattern
0.86mm
0.20mm
C4 (pF)
100
100
22
22
22
12
12
λ3 (mils)
364
100
175
125
89
1.50mm
3.00mm
1.80mm
C7 (pF)
6.8
2.2
1.5
1.5
1.5
1.0
0.5
3.48mm
λ4 (mils)
50
350
275
125
75
0.62mm
1.27mm
ADL5320
L1 (nH)
47
47
15
15
15
15
15