MICRF505YML Micrel Inc, MICRF505YML Datasheet - Page 21

• Manufacturer Part Number: MICRF505YML
• Description: 433/915MHZ ITRANSCEIVER, SMD, MLF32
• Manufacturer: Micrel Inc

Specifications of MICRF505YML

• Transmitting Current: 28mA
• Data Rate: 200Kbps
• Frequency Range: 850MHz To 950MHz
• Modulation Type: FSK
• Sensitivity Dbm: -111dBm
• Rf Ic Case Style: MLF
• No. Of Pins: 32
• Supply Voltage Range: 2V To 2.5V
• Output Power: 10dBm
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

A bit synchronizer can be enabled in receive mode by
selecting the synchronous mode (Sync_en=1). The DataClk-
pin will output a clock with twice the frequency of the bit rate
(a bit rate of 20 kbit/sec gives a DataClk of 20 kHz). A received
symbol/bit on DataIXO will be output on rising edge of
DataClk. The micro controller should therefore sample the
symbol/bit on falling edge of DataClk.
The bit synchronizer uses a clock which needs to be pro-
grammed according to the bit rate. The clock frequency
should be 16 times the actual bit rate (a bit rate of 20 kbit/sec
needs a bit synchronizer clock with frequency of 320 kHz).
The clock frequency is set by the following formula:
The maximum output power is approximately 10dBm for a
50W load. For maximum output power the load seen by the
PA must be resistive. Higher output power can be obtained by
decreasing the load impedance. However, this will be in
conflict with obtaining impedance match in the LNA. The
output power is programmable in seven steps, with approxi-
mately 3dB between each step. This is controlled by bits PA2
- PA0. PA2 - PA0 = 1 give the maximum output power.
The power amplifier can be turned off in by settingPA2 - PA0
= 0.
For all other combinations the PA is on and has a maximum
power when PA2 - PA0 = 1. The PA has 7 power levels in this
case.
The output power vary about 3dB over power supply 2.0V to
2.5V and about 2dB over temperature –40ºC to +85ºC. The
2nd and 3rd harmonic of the PA are as follows:
2nd harmonic: <-25dBm
May 13, 2004
Bit Synchronizer
Transmitter
Power Amplifier
MICRF505
f
BITSYNC_CLK
0000000
0000001
0000110
0000111
A6..A0
A6..A0
=
Refclk_K 2
BitRate_clkS1 BitRate_clkS0
Modulation1 Modulation0
LNA_by
D7
D7
—
¥
f
XCO
(
7 BITSYNC clkS
ModclkS2
-
PA2
D6
D6
_
)
RefClk_K5
ModclkS1
PA1
D5
D5
"0"
RefClk_K4
ModclkS0
21
PA0
D4
D4
"0"
where
Refclk_K is also used to derive the modulator clock and the
bit rate clock.
At the beginning of a received data package, the bit synchro-
nizer clock frequency is not synchronized to the bit rate.
When these two are maximum offset to each other, it takes 22
bit/symbols before synchronization is achieved.
3rd harmonic:
To reduce the emission of harmonics, a LC filter can be added
between the ANT pin and the antenna as shown in Figure 11.
This filter is designed for the 915MHz band with 50Ohm
terminations. The component values may have to be tuned to
compensate for layout parasitics. This filter may also in-
crease the receiver selectivity.
Pin 5
ANT
f
quency
f
Refclk_K:
BitSync_clkS:
BITSYNC_CLK
XCO
BitSync_clkS2 BitSync_clkS1 BitSync_clkS0 BitRate_clkS2
RefClk_K3
RSSI_en
Sync_en
:
D3
D3
<-15dBm
Figure 14. LC Filter
:
RefClk_K2
C7
10pF
The bit synchronizer clock fre-
(16 times higher than the bit rate)
Crystal oscillator frequency
6 bit divider, values between 1
and 63
Bit synchronizer setting, values
between 0 and 7
Mode1
LD_en
D2
D2
4.7nH
L1
RefClk_K1
PF_FC1
Mode0
D1
D1
C8
10pF
M9999-051304
RefClk_K0
Load_en
PF_FC0
D0
D0
Micrel