AD7495ARZ Analog Devices Inc, AD7495ARZ Datasheet - Page 8

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AD7495ARZ

Manufacturer Part Number
AD7495ARZ
Description
Fast 12-Bit Low-power Serial ADC I.C.
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD7495ARZ

Number Of Bits
12
Sampling Rate (per Second)
1M
Data Interface
DSP, MICROWIRE™, QSPI™, Serial, SPI™
Number Of Converters
1
Power Dissipation (max)
10.5mW
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (0.154", 3.90mm Width)
Resolution (bits)
12bit
Sampling Rate
1MSPS
Input Channel Type
Single Ended
Supply Voltage Range - Analogue
2.7V To 5.25V
Supply Voltage Range - Digital
2.7V To 5.25V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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AD7475/AD7495
TIMING EXAMPLE 1
With f
time is t
is 365 ns. The 365 ns satisfies the requirement of 300 ns for t
In Figure 3, t
45 ns. This allows a value of 195 ns for t
minimum requirement of 100 ns.
SCLK
SDATA
2
SCLK
SCLK
+ 12.5(1/f
= 20 MHz and a throughput of 1 MSPS, the cycle
THREE-STATE
CS
CS
ACQ
comprises 2.5(1/f
t
3
SCLK
t
t
2
2
10ns
) + t
0
1
1
FOUR LEADING ZEROS
ACQ
0
= 1 μs. With t
2
2
SCLK
0
) + t
QUIET
3
3
8
+ t
Figure 4. Load Circuit for Digital Output Timing Specifications
2
, satisfying the
0
12.5 (1/f
= 10 ns min, t
QUIET
4
4
TO OUTPUT
, where t
DB11
SCLK
t
Figure 2. Serial Interface Timing Diagram
t
Figure 3. Serial Interface Timing Example
4
t
6
6
)
PIN
5
5
t
CONVERT
t
7
t
DB10
8
CONVERT
ACQ
=
ACQ
50pF
Rev. B | Page 8 of 24
C
.
L
1/THROUGHPUT
200 μ A
200 μ A
13
13
B
B
TIMING EXAMPLE 2
With f
time is t
t
t
t8 = 45 ns. This allows a value of 119 ns for t
minimum requirement of 100 ns. As in this example and with
other slower clock values, the signal may already be acquired
before the conversion is complete, but it is still necessary
to leave 100 ns minimum t
Example 2, the signal should be fully acquired at approximately
Point C in Figure 3.
DB2
ACQ
ACQ
I
I
OL
OH
. In Figure 3, t
is 664 ns. The 664 ns satisfies the requirement of 300 ns for
14
14
t
SCLK
t
5
5
2
DB1
+ 12.5(1/f
1.6V
= 5 MHz and a throughput of 315 KSPS, the cycle
C
15
15
t
t
8
8
DB0
ACQ
45ns
SCLK
16
comprises 2.5(1/f
t
16
ACQUISITION
) + t
THREE-STATE
QUIET
ACQ
= 3.174 μs. With t
between conversions. In
t
t
QUIET
QUIET
SCLK
) + t8 + t
QUIET
2
, satisfying the
= 10 ns min,
QUIET
, where

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