AD8018ARZ Analog Devices Inc, AD8018ARZ Datasheet - Page 10

• Manufacturer Part Number: AD8018ARZ
• Description: SOIC Dual+5V HiSpd Hi Output Current Amp
• Manufacturer: Analog Devices Inc
• Type: Driverr

Specifications of AD8018ARZ

• Number Of Drivers/receivers: 2/0
• Protocol: xDSL
• Voltage - Supply: 3.3 V ~ 8 V
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD8018ARU-EVAL - BOARD EVAL FOR AD8018AD8018AR-EVAL - BOARD EVAL FOR AD8018
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD8018
This circuit requires significant power supply bypassing. The
AD8018 operates on a split supply in this circuit. The bypassing
technique shown in TPC 13 utilizes a 220 F tantalum capacitor
and a 0.1 F ceramic chip capacitor in parallel, connected from
the positive to negative supply, and a 10 F tantalum and 0.1 F
ceramic chip capacitor in parallel, connected from each supply to
ground. The capacitors connected between the power supplies
serve to minimize any voltage ripples that might appear at the
supplies while sourcing or sinking any large differential current.
The large capacitor has a pool of charge instantly available for
the AD8018 to draw from, thus preventing any erroneous dis-
tortion results.
POWER DISSIPATION
It is important to consider the total power dissipation of the
AD8018 in order to properly size the heat sink area of an
application. Figure 8 is a simple representation of a differential
driver. With some simplifying assumptions we can estimate the
total power dissipated in this circuit. If the output current is
large compared to the quiescent current, computing the dissipa-
tion in the output devices and adding it to the quiescent power
dissipation will give a close approximation of the total power
dissipation in the package. A factor
slight error due to the Class A/B operation of the output stage.
It can be estimated by subtracting the quiescent current in the
output stage from the total quiescent current and ratioing that
to the total quiescent current. For the AD8018,
Remembering that each output device dissipates for only half
the time gives a simple integral that computes the power for
each device:
The total supply power can then be computed as:
In this differential driver, V
amplifier, so 2 V
impedance seen by the differential driver, including back termina-
tion. Now, with two observations, the integrals are easily evaluated.
First, the integral of V
V
fied value of V
MAD. It can be shown that for a Discrete MultiTone (DMT)
signal, the MAD value is equal to 0.8 times the rms value.
O
. Second, the integral of |V
P
TOT
4
+V
–V
O
S
S
V
, sometimes called the Mean Average Deviation, or
S
O
is the voltage across R
| |
V
1
2
+V
O
O
O
2
is simply the square of the rms value of
(
V
O
V
S
is the voltage at the output of one
O
–
2
R
V
O
L
| is equal to the average recti-
O
)
R
2
1
L
R
(~0.6-1) corrects for the
V
–V
L
O
L,
O
2
which is the total
I V
Q
+V
–V
= 0.833.
S
S
S
P
OUT
For the AD8018, operating on a single 5 V supply and deliver-
ing a total of 16 dBm (13 dBm to the line and 3 dBm to the
matching network) into 12.5
a 1:4.0 transformer plus back termination), the power is:
Using these calculations, and a
package and 100 C/W for the SOIC, Tables III and IV show
junction temperature versus power delivered to the line for sev-
eral supply voltages.
P
13
14
15
16
17
18
P
13
14
15
16
17
18
Running the AD8018 at voltages near 8 V can produce junction
temperatures that exceed the thermal rating of the TSSOP pack-
ages and should be avoided. The shaded areas indicate junction
temperatures greater than 150 C.
LAYOUT CONSIDERATIONS
As is the case with all high-speed applications, careful attention
to printed circuit board layout details will prevent associated
board parasitics from becoming problematic. Proper RF design
technique is mandatory. The PCB should have a ground plane
covering all unused portions of the component side of the board
to provide a low-impedance return path. Removing the ground
plane on all layers from the area near the input and output pins
will reduce stray capacitance, particularly in the area of the
inverting inputs. Signal lines connecting the feedback and gain
resistors should be as short as possible to minimize the inductance
and stray capacitance associated with these traces. Termination
resistors and loads should be located as close as possible to their
respective inputs and outputs. Input and output traces should
be kept as far apart as possible to minimize coupling (crosstalk)
though the board. Adherence to stripline design techniques for
long signal traces (greater than about 1 inch) is recommended.
LINE,
LINE,
P
TOT
Table III. Junction Temperature vs. Line Power and
Operating Voltage for TSSOP, T
Table IV. Junction Temperature vs. Line Power and
Operating Voltage for SOIC, T
dBm 5
dBm
4 0 8
( .
115
117
119
121
123
125
V rmsV
5
111
113
115
116
118
120
O
= 261 mW + 40 mW
S
–
= 301 mW
V rms
6
122
125
127
130
133
136
O
JA
V
6
117
119
122
124
127
130
(100
V
SUPPLY
of 115 C/W for the TSSOP
SUPPLY
2
AMB
)
AMB
R
= 85 C
1
reflected back through
L
= 85 C
7
129
132
136
139
143
147
2
7
123
126
129
132
136
139
I V
Q
S
P
OUT
8
136
140
144
148
153
158
8
129
133
136
140
144
149