FM31L278-G Ramtron, FM31L278-G Datasheet
FM31L278-G
Specifications of FM31L278-G
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FM31L278-G Summary of contents
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... Pre-Production FM31L278/L276/L274/L272 3V Integrated Processor Companion with Memory Features High Integration Device Replaces Multiple Parts • Serial Nonvolatile Memory • Real-time Clock (RTC) • Low Voltage Reset • Watchdog Timer • Early Power-Fail Warning/NMI • Two 16-bit Event Counters • Serial Number with Write-lock for Security Ferroelectric Nonvolatile RAM • ...
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... Device Select inputs Clock Calibration and Early Power-Fail Output Reset Input/Output Early Power-fail Input Crystal Connections Serial Data Serial Clock Battery-Backup Supply Supply Voltage Ground Ordering Part Number FM31L278-G FM31L278-GTR (tape&reel) FM31L276-G FM31L276-GTR (tape&reel) FM31L274-G FM31L274-GTR (tape&reel) FM31L272-G FM31L272-GTR (tape&reel) Page ...
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... VBC bit should be cleared. The trickle charger is UL recognized and ensures no excessive current when using a lithium battery. VDD Supply Supply Voltage VSS Supply Ground Rev. 2.0 Jan. 2011 FM31L278/L276/L274/L272 - 3V I2C Companion Special Function Watchdog Registers LV Detect S/N RTC Cal. 1.2V 512Hz ...
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... Based on the setting, the protected addresses cannot be written and the 2-wire interface will not acknowledge any data to Rev. 2.0 Jan. 2011 FM31L278/L276/L274/L272 - 3V I2C Companion protected addresses. The special function registers containing these bits are described in detail below. Write protect addresses None ...
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... Watchdog timeout Figure 3. Watchdog Timer Rev. 2.0 Jan. 2011 FM31L278/L276/L274/L272 - 3V I2C Companion Manual Reset The /RST pin is bi-directional and allows the FM31L27x to filter and de-bounce a manual reset switch. The /RST input detects an external low condition and responds by driving the /RST signal low for 100 ms ...
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... CC Figure 6. Event Counter Rev. 2.0 Jan. 2011 FM31L278/L276/L274/L272 - 3V I2C Companion The control bits for event counting are located in register 0Ch. Counter 1 Polarity is bit C1P, bit 0; Counter 2 Polarity is C2P, bit 1; the Cascade Control is CC, bit 2; and the Read Counter bit is RC bit 3. ...
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... Figure 8. V (min.) vs. Temperature BAK Rev. 2.0 Jan. 2011 FM31L278/L276/L274/L272 - 3V I2C Companion Trickle Charger To facilitate capacitor backup the V optionally provide a trickle charge current. When the VBC bit, register 0Bh bit 2, is set to ‘1’, the V will source approximately 80 µA until V V ...
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... The FM31L27x device has built-in loading capacitors that match the crystal 32.768kHz crystal is not used, an external oscillator may be connected to the FM31L27x. Rev. 2.0 Jan. 2011 FM31L278/L276/L274/L272 - 3V I2C Companion /OSCEN Clock Oscillator Divider Date 6 bits ...
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... SCL SDA X2 X1 PFI VBAK Layout for Surface Mount Crystal (red = top layer, green = bottom layer) Rev. 2.0 Jan. 2011 FM31L278/L276/L274/L272 - 3V I2C Companion VDD SCL SDA X2 X1 PFI VBAK Layout for Through Hole Crystal (red = top layer, green = bottom layer) Page ...
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... Rev. 2.0 Jan. 2011 FM31L278/L276/L274/L272 - 3V I2C Companion Error Range (PPM) Min Max Program Calibration Register to: 0 2.17 2.18 6.51 6.52 10.85 10.86 15.19 15.20 19.53 19.54 23.87 23.88 28.21 28 ...
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... Note: When the device is first powered up and programmed, all registers must be written because the battery- backed register values cannot be guaranteed. The table below shows the default values of the non-volatile registers. All other register values should be treated as unknown. Rev. 2.0 Jan. 2011 FM31L278/L276/L274/L272 - 3V I2C Companion ...
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... C1.15 C1.14 Event Counter 1 MSB. Increments on overflows from Counter 1 LSB. Battery-backed, read/write. 0Dh Counter 1 LSB D7 D6 C1.7 C1.6 Event Counter 1 LSB. Increments on programmed edge event on CNT1 input. Battery-backed, read/write. Rev. 2.0 Jan. 2011 FM31L278/L276/L274/L272 - 3V I2C Companion SN.61 SN.60 SN. SN.53 SN.52 SN.51 ...
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... WR3-0. Nonvolatile, read/write. Watchdog timeout Invalid – default 100 ms 100 ms 200 ms 300 2000 ms 2100 ms 2200 2900 ms 3000 ms Disable counter Rev. 2.0 Jan. 2011 FM31L278/L276/L274/L272 - 3V I2C Companion WP1 WP0 WP1 WP0 ...
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... Contains the BCD value of seconds. Lower nibble contains the lower digit and operates from upper nibble contains the upper digit and operates from The range for the register is 0-59. Battery-backed, read/write. Rev. 2.0 Jan. 2011 FM31L278/L276/L274/L272 - 3V I2C Companion WR3 < ...
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... The user can then read them without concerns over changing values causing system errors. The R bit going from causes the timekeeping capture, so the bit must be returned to 0 prior to reading again. Battery-backed, read/write. Reserved Reserved bits. Do not use. Should remain set to 0. Rev. 2.0 Jan. 2011 FM31L278/L276/L274/L272 - 3V I2C Companion CALS CAL.4 CAL.3 ...
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... SDA signal should not change while SCL is high. Rev. 2.0 Jan. 2011 FM31L278/L276/L274/L272 - 3V I2C Companion By convention, any device that is sending data onto the bus is the transmitter while the target device for this data is the receiver. The device that is controlling the bus is the master ...
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... Rev. 2.0 Jan. 2011 FM31L278/L276/L274/L272 - 3V I2C Companion Following the MSB is the LSB (lower byte) which contains the remaining eight address bits. The address is latched internally. Each access causes the latched address to be incremented automatically ...
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... Thus, a sequential read is simply a current address read with multiple byte transfers. After each byte the internal address counter will be incremented. Rev. 2.0 Jan. 2011 FM31L278/L276/L274/L272 - 3V I2C Companion below illustrate a single- and multiple-writes to memory. Address & Data A Address MSB ...
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... Slave Address 1 By FM31L27x Rev. 2.0 Jan. 2011 FM31L278/L276/L274/L272 - 3V I2C Companion master supplies a Slave Address with the LSB set to 1. This indicates that a read operation is requested. After receiving the complete Slave Address, the FM31L27x will begin shifting data out from the current register address on the next clock ...
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... Table 4. Two-Byte Memory Address st Part # 1 FM31L278 x A14 A13 FM31L276 FM31L274 FM31L272 Rev. 2.0 Jan. 2011 FM31L278/L276/L274/L272 - 3V I2C Companion Address Start A Address LSB A S Slave Address 1 Acknowledge Address & Data Address Acknowledge Figure 19. Byte Register Write Address Byte A12 A11 A10 A9 A8 ...
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... CNT1-2 (V > 2.5V Input High Voltage IH All inputs except those listed below PFI (comparator input) CNT1-2 battery backed (V CNT1-2 V > 2.5V DD Rev. 2.0 Jan. 2011 FM31L278/L276/L274/L272 - 3V I2C Companion 2.7V to 3.6V unless otherwise specified) DD Min 2.7 1.55 1.9 =0V BAK 50 200 2.55 2. µ ...
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... Input/Output Capacitance IO C X1, X2 Crystal pin Capacitance XTAL Notes 1 This parameter is characterized but not tested. 2 The crystal attached to the X1/X2 pins must be rated as 12.5pF. Rev. 2.0 Jan. 2011 FM31L278/L276/L274/L272 - 3V I2C Companion (T = -40° 85° 2.7V to 3.6V unless otherwise specified Min = 3 mA mA) 2.4 50 ...
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... Timing VDD VTP VRST t RNR RST Data Retention (V = 2.7V to 3.6V) DD Symbol Parameter T Data Retention DR @ +75°C @ +80°C @ +85°C Rev. 2.0 Jan. 2011 FM31L278/L276/L274/L272 - 3V I2C Companion = 2.7V to 3.6V) DD Min >V 100 DD TP 100 100 t waveform. > V and t satisfied RPU t RPU Min ...
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... Functional relationships are illustrated in the relevant data sheet sections. These diagrams illustrate the timing parameters only. Read Bus Timing SCL t t SU:STA BUF SDA Start Write Bus Timing SCL t SU:STO SDA Start Rev. 2.0 Jan. 2011 FM31L278/L276/L274/L272 - 3V I2C Companion HIGH 1/f SCL t AA ...
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... XXXXXX= part number, P= package type (G=”Green”/RoHS) R=rev, LLLLLLL= lot code RIC=Ramtron Int’l Corp, YY=year, WW=work week FM31L278-G D70023G RIC 1106 Recommended PCB Footprint . . . 7.70 3. 0.65 1.27 0.25 0.50 0.19 ° ...
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... Revision History Revision Date 2.0 1/31/2011 Rev. 2.0 Jan. 2011 FM31L278/L276/L274/L272 - 3V I2C Companion Summary Pre-Production. Rev D. Changed I Backup Power section (p.7). and V specs. Added curves to BAK BAK Page ...