SST39VF1601-70-4I-EKE SILICON STORAGE TECHNOLOGY, SST39VF1601-70-4I-EKE Datasheet - Page 17
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SST39VF1601-70-4I-EKE
Manufacturer Part Number
SST39VF1601-70-4I-EKE
Description
MEMORY, FLASH, 16MBIT, B/B, 48TSOP
Manufacturer
SILICON STORAGE TECHNOLOGY
Datasheet
1.SST39VF1601-70-4I-EKE.pdf
(31 pages)
Specifications of SST39VF1601-70-4I-EKE
Memory Size
16Mbit
Supply Voltage Range
2.7V To 3.6V
Memory Case Style
TSOP
No. Of Pins
48
Operating Temperature Range
-40°C To +85��C
Svhc
No SVHC (18-Jun-2010)
Access Time
70ns
Memory Type
Flash - NOR
Memory Configuration
1M X 16
Interface Type
CFI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SST39VF1601-70-4I-EKE
Manufacturer:
SST44
Quantity:
51
Part Number:
SST39VF1601-70-4I-EKE
Manufacturer:
SST
Quantity:
20 000
16 Mbit / 32 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201
SST39VF1602 / SST39VF3202
©2008 Silicon Storage Technology, Inc.
FIGURE 8: Toggle Bits Timing Diagram
FIGURE 9: WE# Controlled Chip-Erase Timing Diagram
ADDRESS A
ADDRESS A
ADDRESS A
DQ
DQ
DQ
6
and DQ
WE#
WE#
MS-0
MS-0
OE#
OE#
CE#
CE#
15-0
15-0
WE#
MS-0
OE#
CE#
2
Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are
Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are
Note:
5555
5555
interchageable as long as minimum timings are met. (See Table 17)
A
interchageable as long as minimum timings are met. (See Table 17)
A
A
WP# must be held in proper logic state (V
A
X can be V
WP# must be held in proper logic state (V
X can be V
XXAA
XXAA
SW0
SW0
T
T
MS
MS
MS
MS
A
A
WP
WP
MS
MS
= Most significant address
= A
= Most significant address
= A
= Most significant address
= A
19
19
2AAA
2AAA
IL
IL
for SST39VF1601/1602 and A
for SST39VF1601/1602 and A
19
or V
or V
T
XX55
XX55
for SST39VF1601/1602 and A
SW1
SW1
OEH
IH
IH
, but no other value
, but no other value
SIX-BYTE CODE FOR CHIP-ERASE
SIX-BYTE CODE FOR CHIP-ERASE
T
CE
5555
5555
XX80
XX80
SW2
SW2
T
OE
5555
5555
17
XXAA
XXAA
SW3
SW3
20
20
IH
IH
) 1 µs prior to and 1 µs after the command sequence
) 1 µs prior to and 1 µs after the command sequence
for SST39VF3201/3202
for SST39VF3201/3202
20
for SST39VF3201/3202
2AAA
2AAA
XX55
XX55
SW4
SW4
5555
5555
XX10
XX10
SW5
SW5
WITH SAME OUTPUTS
TWO READ CYCLES
T
T
SCE
SCE
S71223-05-000
T
OES
1223 F07.4
Data Sheet
1223 F08.5
1223 F08.5
6/08