CS4360-KZ Cirrus Logic Inc, CS4360-KZ Datasheet
CS4360-KZ
Specifications of CS4360-KZ
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CS4360-KZ Summary of contents
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... These features are ideal for cost-sensitive, multi-channel audio systems in- cluding DVD players, A/V receivers, set-top boxes, digital TVs and VCRs, mini-component systems, and mixing consoles. ORDERING INFORMATION CS4360-KS CS4360-BS CS4360-KZ CS4360-BZ CDB4360 M2 VLC lati ilt olu ...
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... The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com. 2 CS4360 DS517PP1 ...
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... Figure 13. High-Rate Transition Band (Detail) .............................................................................. 28 Figure 14. High-Rate Passband Ripple ......................................................................................... 28 Figure 15. Output Test Load ......................................................................................................... 28 Figure 16. Maximum Loading ........................................................................................................ 28 Figure 17. CS4360 Format 0 - Left Justified upto 24-bit Data ....................................................... 29 Figure 18. CS4360 Format Figure 19. CS4360 Format 2 - Right Justified 16-bit Data ............................................................ 29 Figure 20. CS4360 Format 3 - Right Justified 24-bit Data ............................................................ 29 Figure 21 ...
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... Figure 22. CS4360 Format 5 - Right Justified 18-bit Data ............................................................ 30 Figure 23. De-Emphasis Curve ..................................................................................................... 30 Figure 24. ATAPI Block Diagram .................................................................................................. 31 LIST OF TABLES Table 1. Digital Interface Formats - Control Port Mode .................................................................... 14 Table 2. ATAPI Decode.................................................................................................................... 16 Table 3. Example Digital Volume Settings ....................................................................................... 17 Table 4. Digital Interface Formats - Stand Alone Mode.................................................................... 21 Table 5. Mode Selection................................................................................................................... 21 Table 6 ...
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... Interchannel Isolation Notes: 1. CS4360-KS/-KZ parts are tested at 25 °C. 2. One-half LSB of triangular PDF dither is added to data. 3. CS4360-BS/-BZ parts are tested at the extremes of the specified temperature range and Min/Max performance numbers are guaranteed across the specified temperature range, T taken at 25 °C. ANALOG CHARACTERISTICS ...
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... Refer to Figure 16. 6 Symbol Min (Note 6) tgd kHz kHz Fs = 44.1 kHz kHz kHz Fs = 44.1 kHz kHz (Note 5) to -0.1 dB corner corner -0.1 .577 (Note 6) tgd kHz (Note corner -0.7 tgd Symbol 0.60• (Note OUT CS4360 Typ Max Unit 9/ ±0.36/ +.2/-. +.05/-. +0/-. +1.5/- +.05/-. ...
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... SOIC (-KS & -BS TSSOP (-KZ & -BZ (Note 12) PSRR (60 Hz) PSRR (For -KS & -KZ parts T A Symbol V Serial Audio Data Port IH V Control Port IH V Serial Audio Data Port Control Port CS4360 Min Typ Max - 0.002 - - 0.002 - - 0.016 - - 235 TBD - 0.080 ...
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... Analog Power VA Digital Power VD VLS VLC Min Max -0.3 6.0 -0.3 6.0 -0.3 6.0 -0.3 6.0 - ±10 in -0.3 VLS + 0.4 -0.3 VLC + 0.4 -55 125 A -65 150 Min Typ Max 2.7 5 5.5 2 1.8 5 5.5 1.8 5 5.5 CS4360 Units °C °C Units DS517PP1 ...
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... T Symbol Single-Speed Mode F s Double-Speed Mode F s Quad-Speed Mode F s Note 15 t slrd t slrs t sdlrs t sdh t slrs t sdlrs Figure 1. Serial Mode Input Timing CS4360 = -10 to +70°C; for -BS & -BZ parts T A Min Typ Max 100 100 - 200 MCLK MCLK/4 ...
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... SCL for Quad-Speed Mode. ----------------- - ate d Sta hdst t sust t rc CS4360 Unit kHz ns µs µs µs µs µs µs ns µs ns µs ns Stop susp DS517PP1 ...
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... Symbol f sclk t srs (Note 20) t spi t csh t css t scl t sch t dsu (Note 21 (Note 22 (Note 22 srs t spi t css t scl t sch dsu t dh Figure 3. Control Port Timing - SPI Format CS4360 Min Max Unit - 6 MHz 500 - ns 500 - ns 1.0 - µ 100 ns - 100 all other times. ...
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... RST AOUT3A + 3.3 µF DIF1/SCL/CCLK DIF0/SDA/CDIN 19 M1/AD0/CS AOUT3B + M2 3.3 µF 18 MUTEC3 VLC 16 FILT 0.1 µ F GND GND 9 21 Figure 4. Typical Connection Diagram CS4360 + µF * All supplies can be tied together 560 OPTIONAL 560 MUTE CIRCUIT 560 OPTIONAL 560 MUTE CIRCUIT 560 OPTIONAL ...
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... B3_MUTE B3_VOL6 B3_VOL5 B3_VOL4 B3_VOL3 B3_VOL2 B3_VOL1 B3_VOL0 0 default 0Ch Mode Control 2 SZC1 1 default 0Dh Revision Indicator Reserved Reserved Reserved Reserved 0 default DS517PP1 DIF2 DIF1 DIF0 DEM1 INV_B3 INV_A3 INV_B2 SZC0 CPEN PDN POPG REV3 CS4360 DEM0 FM1 FM0 INV_A2 INV_B1 INV_A1 FREEZE MCLKDIV SNGLVOL REV2 REV1 REV0 X X ...
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... Table 1. Digital Interface Formats - Control Port Mode DIF1 DIF0 DEM1 DIF0 DESCRIPTION 0 Left Justified 24-bit data 24-bit data 0 Right Justified, 16-bit data 1 Right Justified, 24-bit data 0 Right Justified, 20-bit data 1 Right Justified, 18-bit data 0 Reserved 1 Reserved CS4360 DEM0 FM1 FM0 Format FIGURE DS517PP1 ...
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... When enabled, these bits invert the signal polarity for each of their respective channels. 4.3 Mixing Control Pair 1 (Channels A1 & B1) (address 03h) Mixing Control Pair 2 (Channels A2 & B2) (address 04h) Mixing Control Pair 3 (Channels A3 & B3) (address 05h Reserved Reserved Reserved 0 0 DS517PP1 INV_A3 INV_B2 Reserved PxATAPI3 CS4360 INV_A2 INV_B1 INV_A1 PxATAPI2 PxATAPI1 PxATAPI0 ...
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... ATAPI CHANNEL MIXING AND MUTING (ATAPI) Default = 1001 - AOUTAx = L, AOUTBx = R (Stereo) Function: The CS4360 implements the channel mixing functions of the ATAPI CD-ROM specification. Refer to Table 2 and Figure 24 for additional information. Note: All mixing functions occur prior to the digital volume control. Mixing only occurs in channel pairs. ...
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... The zero cross func- tion is independently monitored and implemented for each channel. DS517PP1 (XX_VOL) Decimal Value Volume Setting 0 -20 -20 dB -40 -40 dB -60 -60 dB -90 - CPEN PDN POPG FREEZE MCLKDIV 0 0 CS4360 0 SNGLVOL 0 17 ...
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... FREEZE bit, make all register changes, then disable the FREEZE bit. 4.5.6 MASTER CLOCK DIVIDE ENABLE (MCLKDIV) Default = Disabled 1 - Enabled Function: The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all other internal circuitry. 18 CS4360 DS517PP1 ...
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... Revision Register (Read Only) (address 0Dh Reserved Reserved Reserved 0 0 4.6.1 REVISION INDICATOR (REV) [READ ONLY] Default = none 0001 - Revision A 0010 - Revision B 0011 - Revision C etc. Function: This read-only register indicates the revision level of the device. DS517PP1 Reserved REV3 CS4360 REV2 REV1 REV0 ...
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... AOUTB1 Analog Output SDIN3 MUTEC2 Mute Control SCLK AOUTA2 Analog Output LRCK AOUTB2 Analog Output MCLK GND 8 21 GND AOUTA3 Analog Output RST AOUTB3 Analog Output MUTEC3 Mute Control FILT VLC CS4360 Analog Power Ground Quiescent Voltage Positive Voltage Reference Mode 2 DS517PP1 ...
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... Right Justified, 24-bit data Table 4. Digital Interface Formats - Stand Alone Mode M1 0 Single-Speed without de-emphasis ( kHz sample rates) 1 Single-Speed with de-emphasis ( kHz sample rates) 0 Double-Speed (50 to 100 kHz sample rates) 1 Quad-Speed (100 to 200 kHz sample rates) Table 5. Mode Selection CS4360 DESCRIPTION MODE 21 ...
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... MCLK (MHz) 512x 768x 1024x* 16.3840 24.5760 32.7680 22.5792 32.7680 45.1584 24.5760 36.8640 49.1520 MCLK (MHz) 256x 384x 512x* 16.3840 24.5760 32.7680 22.5792 33.8688 45.1584 24.5760 36.8640 49.1520 MCLK (MHz) 128x 192x 256x* 22.5792 33.8688 45.1584 24.5760 36.8640 49.1520 CS4360 DS517PP1 ...
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... Popguard Transient Control The CS4360 uses a novel technique to minimize the effects of output transients during power-up and power-down. This technique, when used with external DC-blocking capacitors in series with the audio outputs, minimizes the audio transients com- monly produced by single-ended single-supply converters ...
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... The control port has 2 formats: SPI and Two-Wire, with the CS4360 operating as a slave device. If Two-Wire operation is desired, AD0/CS should be tied to VLS or GND. If the CS4360 ever detects a high to low transition on AD0/CS after power-up and after the control port is activated, SPI format will be selected ...
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... To end the transaction, send a STOP condi- tion. 7.4 SPI Format In SPI format the CS4360 chip select signal, CCLK is the control port bit clock, CDIN is the in- put data line from the microcontroller and the chip address is 0010000. CS, CCLK and CDIN are all ...
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... Memory Address Pointer (MAP INCR Reserved Reserved 0 0 7.5.1 INCR (AUTO MAP INCREMENT ENABLE) Default = ‘0’ Disabled 1 - Enabled 7.5.2 MAP (MEMORY ADDRESS POINTER) Default = ‘0000’ Reserved MAP3 CS4360 MAP2 MAP1 MAP0 DS517PP1 ...
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... Figure 7. Base-Rate Stopband Rejection Figure 9. Base-Rate Transition Band (Detail) Figure 11. High-Rate Stopband Rejection DS517PP1 Figure 8. Base-Rate Transition Band Figure 10. Base-Rate Passband Ripple Figure 12. High-Rate Transition Band CS4360 27 ...
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... Figure 13. High-Rate Transition Band (Detail) AGND 125 100 75 Safe Operating 50 Region 25 2 Resistive Load -- R Figure 16. Maximum Loading 28 Figure 14. High-Rate Passband Ripple 3.3 µF + AOUTx R L Figure 15. Output Test Load CS4360 V out C L DS517PP1 ...
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... Left Channel LRCK SCLK SDINx Figure 17. CS4360 Format 0 - Left Justified up to 24-bit Data Left Channel LRCK SCLK SDINx LRCK Left Channel SCLK SDINx clocks Figure 19. CS4360 Format 2 - Right Justified 16-bit Data LRCK Left Channel SCLK SDINx clocks Figure 20. CS4360 Format 3 - Right Justified 24-bit Data ...
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... LRCK Left Channel SCLK SDINx clocks Figure 21. CS4360 Format 4 - Right Justified 20-bit Data LRCK Left Channel SCLK SDINx clocks Figure 22. CS4360 Format 5 - Right Justified 18-bit Data Gain dB T1=50 µs 0dB -10dB F1 F2 3.183 kHz 10.61 kHz Figure 23. De-Emphasis Curve Right Channel ...
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... Left Channel Audio Data Right Channel Audio Data DS517PP1 A Channel Volume Control & Mute B Channel Volume Control & Mute Figure 24. ATAPI Block Diagram CS4360 AoutA AoutB 31 ...
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... Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters” by Steven Harris. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992. 2) CDB4360 Evaluation Board Datasheet 2 3) “The I C Bus Specification: Version 2.0” Philips Semiconductors, December 1998. http://www.semiconductors.philips.com 32 CS4360 DS517PP1 ...
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... JEDEC #: MS-013 Controlling Dimension is Millimeters CS4360 MILLIMETERS MIN NOM 2.35 2.50 0.10 0.20 0.33 0.42 0.23 0.28 17.70 17.90 18.10 7.40 7 ...
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... JEDEC #: MO-153 Controlling Dimension is Millimeters END VIEW L PLANE MILLIMETERS NOM MAX -- -- 1.20 0.10 0.15 0.90 1.00 0.245 0.30 9.70 BSC 9.80 BSC 6.40 6.50 4.40 4.50 -- 0.65 BSC -- 0.60 0.75 0° 4° 8° CS4360 NOTE 2 DS517PP1 ...
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Notes • ...
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