CS61884-IQZ Cirrus Logic Inc, CS61884-IQZ Datasheet - Page 32

• Manufacturer Part Number: CS61884-IQZ
• Description: IC,PCM TRANSCEIVER,OCTAL,CEPT PCM-30/E-1,QFP,144PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS61884-IQZ

• Rohs Compliant: YES

13. HOST MODE
Host mode allows the CS61884 to be configured
and monitored using an internal register set. (Refer
to
page
Parallel Host and Serial Host modes.
All of the internal registers are available in both Se-
rial and Parallel Host mode; the only difference is
in the functions of the interface pins, which are de-
scribed in
Serial port operation is compatible with the serial
ports of most microcontrollers. Parallel port opera-
tion can be configured to be compatible with 8-bit
microcontrollers from Motorola or Intel, with both
multiplexed or non-multiplexed address/data bus-
ses. (Refer to
registers).
13.1 SOFTWARE RESET
A software reset can be forced by writing the
ware Reset Register (0Ah)
page 36). A software reset initializes all registers to
their default settings and initializes all internal state
machines.
32
Table 1, “Operation Mode Selection,” on
LOOP[7:0], DATA[7:0]
10). The term, “Host mode” applies to both
LEN2/SCLK/AS/ALE
CODEN/MOT/INTL
LEN0/SDI/DS/WR
SDO/ACK/RDY
LEN1/R/W/RD
PIN NAME
ADDR[3:0]
JASEL/CS
Table
ADDR [4]
MODE
MUX
INT
Table 9 on page 34
8.
(See Section 14.11 on
HOST CONTROL SIGNAL DESCRIPTIONS
PIN #
13-16
28-21
Table 8. Host Control Signal Descriptions
43
88
12
82
83
84
85
86
87
11
for host mode
Soft-
HARDWARE
ADDR[3:0]
LOOP[7:0]
Pulled Up
BITSEN0
CODEN
JASEL
LEN0
LEN1
LEN2
LOW
GND
NC
13.2 Serial Port Operation
Serial port host mode operation is selected when
the MODE pin is left open or set to VCC/2. In this
mode, the CS61884 register set is accessed by set-
ting the chip select (CS) pin low and communicat-
ing over the SDI, SDO, and SCLK pins. Timing
over the serial port is independent of the transmit
and receive system timing.
format of serial port data transfers.
A read or write is initiated by writing an ad-
dress/command byte (ACB) to SDI. Only the
ADR0-ADR4 bits are valid; bits ADR5-ADR6 are
do not cares. During a read cycle, the register data
addressed by the ACB is output on SDO on the next
eight SCLK clock cycles. During a write cycle, the
data byte immediately follows the ACB.
Data is written to and read from the serial port in
LSB first format. When writing to the port, SDI
data is sampled by the device on the rising edge of
SCLK. The valid clock edge of the data on SDO is
controlled by the CLKE pin. When CLKE is low,
data on SDO is valid on the falling edge of SCLK.
When CLKE is high, data on SDO is valid on the
raising edge of SCLK. The SDO pin is Hi-Z when
not transmitting. If the host processor has a bidirec-
tional I/O port, SDI and SDO may be tied together.
SERIAL
VDD/2
SCLK
SDO
INT
SDI
CS
-
-
-
-
-
-
Figure 13
PARALLEL
ADDR [3:0]
MOT/INTL
DATA[7:0]
ACK/RDY
ADDR[4]
R/W/RD
AS/ALE
DS/WR
HIGH
MUX
CS61884
INT
illustrates the
CS
DS485F1