DS90C387VJD National Semiconductor, DS90C387VJD Datasheet
DS90C387VJD
Specifications of DS90C387VJD
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DS90C387VJD Summary of contents
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... LVDS technology that delivers the bandwidth needed for high-resolution panels TRI-STATE ® registered trademark of National Semiconductor Corporation. © 2006 National Semiconductor Corporation while maximizing bit times, and keeping clock rates low to reduce EMI and shielding requirements. For more details, please refer to the “ ...
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Transmitter Block Diagram Receiver Block Diagram Generalized Block Diagram www.national.com 10007302 10007303 10007301 2 ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( CMOS/TTL Input Voltage CMOS/TTL Output Voltage −0. LVDS Receiver Input Voltage LVDS Driver Output Voltage LVDS Output Short Circuit ...
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Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter TRANSMITTER SUPPLY CURRENT ICCTW Transmitter Supply Current Worst Case ICCTG Transmitter Supply Current 16 Grayscale ICCTZ Transmitter Supply Current Power Down RECEIVER SUPPLY CURRENT ICCRW Receiver ...
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Recommended Transmitter Input Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol TCIT TxCLK IN Transition Time (Figure 5) TCIP TxCLK IN Period (Figure 6) TCIH TxCLK in High Time (Figure 6) TCIL TxCLK in Low Time ...
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Receiver Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol RPLLS Receiver Phase Lock Loop Set (Figure 9) RPDD Receiver Powerdown Delay (Figure 11) Chipset RSKM Characteristics Over recommended operating supply and temperature ranges unless otherwise ...
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AC Timing Diagrams FIGURE 2. “16 Grayscale” Test Pattern (Notes 9, 10, 11) Note 9: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O. Note 10: The 16 grayscale test pattern tests ...
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AC Timing Diagrams FIGURE 3. DS90C387 (Transmitter) LVDS Output Load and Transition Times FIGURE 4. DS90CF388 (Receiver) CMOS/TTL Output Load and Transition Times FIGURE 5. DS90C387 (Transmitter) Input Clock Transition Time FIGURE 6. DS90C387 (Transmitter) Setup/Hold and High/Low Times (Falling ...
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AC Timing Diagrams (Continued) FIGURE 7. DS90CF388 (Receiver) Setup/Hold and High/Low Times FIGURE 8. DS90C387 (Transmitter) Phase Lock Loop Set Time FIGURE 9. DS90CF388 (Receiver) Phase Lock Loop Set Time 10007316 10007319 9 10007320 www.national.com ...
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AC Timing Diagrams www.national.com (Continued) FIGURE 10. Transmitter Power Down Delay FIGURE 11. Receiver Power Down Delay 10 10007321 10007322 ...
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AC Timing Diagrams (Continued) C — Setup and Hold Time (Internal data sampling window) defined by RSPOS (receiver input strobe position) min and max TPPOS — Transmitter output pulse position (min and max) RSKM ≥ Cable Skew (type, length) + ...
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AC Timing Diagrams FIGURE 15. Timing Diagram of the Input Cycle-to-Cycle Clock Jitter www.national.com (Continued) FIGURE 14. TJCC Test Setup - DS90C387 12 10007327 10007328 ...
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DS90C387 Pin Descriptions — FPD Link Transmitter Pin Name I/O No. Rn, Gn, Bn DE, HSYNC, VSYNC AnP O 8 AnM O 8 CLKIN I 1 R_FB I 1 R_FDE I 1 CLK1P O 1 CLK1M O 1 ...
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DS90CF388 Pin Descriptions — FPD Link Receiver Pin Name I/O AnP I AnM I Rn, Gn, Bn, O DE, HSYNC, VSYNC RxCLK INP I RxCLK INM I RxCLK OUT O R_FDE I PLLSEL I BAL I DESKEW ...
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LVDS Interface Different Color Mapping options exists. Please see National Application Notes 1127 and AN-1163 for details. A careful review of Color Mapping information is recommended as TABLE 1. LVDS DATA BIT NAMING CONVENTION X=R X=G X=B ...
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LVDS Interface (Continued) TABLE 3. DUAL PIXEL PER CLOCK INPUT APPLICATION DATA MAPPING (DUAL=VCC) (Continued) VGA - TFT Data Signals Color Bits RO3 RO1 RO4 RO2 RO5 RO3 RO6 RO4 MSB RO7 RO5 LSB GO0 GO1 GO2 GO0 GO3 GO1 ...
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LVDS Interface (Continued) TABLE 4. SINGLE PIXEL PER CLOCK INPUT-TO-DUAL PIXEL PER CLOCK OUTPUT DATA MAPPING (DUAL=1/2VCC) VGA - TFT Data Signals Color Transmitter input pin names Bits 24-bit 18-bit LSB ...
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LVDS Interface (Continued) TABLE 4. SINGLE PIXEL PER CLOCK INPUT-TO-DUAL PIXEL PER CLOCK OUTPUT DATA MAPPING VGA - TFT Data Signals Color Bits Note that redundant copies of certain signals are also sent. These signals are denoted with an * ...
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LVDS Interface (Continued) Note that the LVDS Clock signal is also DC Balanced in this mode. The rising edge location is fixed, but the location of the falling edge will be in one of two locations as shown above. Optional ...
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LVDS Interface (Continued) FIGURE 19. Control Signals Transmitted During Blanking Note 18: The control signal during blanking shown above is for R_FDE=High, when R_FDE=Low all the low/high patterns are reversed. www.national.com Control Signals Transmitted During Blanking 20 10007305 10007309 ...
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Applications Information HOW TO CONFIGURE THE DS90C387 AND DS90CF388 FOR MOST COMMON APPLICATION 1. To configure for single input pixel-to-dual pixel output application, the DS90C387 “DUAL” pin must be set to 1/2 Vcc=1.65V. This may be implemented using pull-up and ...
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Applications Information plus the inverse of the calculated data disparity if the data is sent inverted. The value of the running word disparity shall saturate at +7 and −6. The value of the DC Balance bit (DCBAL) shall be 0 ...
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Applications Information Timing and control signals (VSYNC, HSYNC, DE and two user-defined signals) are sent during blanking intervals to guarantee correct reception of these critical signals. The transmitter is offered with programmable edge data strobes for convenient interface with a ...
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Pin Diagrams www.national.com Transmitter-DS90C387 24 10007306 ...
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Pin Diagrams (Continued) Receiver-DS90CF388 25 10007307 www.national.com ...
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... Physical Dimensions inches (millimeters) unless otherwise noted Order Number DS90C387VJD and DS90CF388VJD National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. ...