DS90CF364AMTD National Semiconductor, DS90CF364AMTD Datasheet
DS90CF364AMTD
Specifications of DS90CF364AMTD
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DS90CF364AMTD Summary of contents
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... PLL requires no external components ■ Compatible with TIA/EIA-644 LVDS standard ■ Low profile 56-lead or 48-lead TSSOP package ■ DS90CF384A is also available ball, 0.8mm fine pitch ball grid array (FBGA) package 10087027 Order Number DS90CF364AMTD See NS Package Number MTD48 100870 July 2007 DS90CF364A 10087028 www.national.com ...
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... IN RECEIVER SUPPLY CURRENT ICCRW Receiver Supply Current Worst Case ICCRW Receiver Supply Current Worst Case www.national.com SLC (FBGA) Package: (Note 1) DS90CF384A Package Derating: DS90CF384AMTD DS90CF364AMTD −0.3V to +4V DS90CF384ASLC −0. 0.3V) CC ESD Rating −0. 0.3V) CC (HBM, 1.5 kΩ, 100 pF) −0. 0.3V) CC (EIAJ, 0Ω, 200 pF) +150° ...
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Symbol Parameter ICCRG Receiver Supply Current, 16 Grayscale ICCRZ Receiver Supply Current Power Down Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the ...
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AC Timing Diagrams FIGURE 2. “16 Grayscale” Test Pattern (DS90CF384A)(Notes www.national.com FIGURE 1. “Worst Case” Test Pattern 4 10087002 10087012 ...
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FIGURE 3. “16 Grayscale” Test Pattern (DS90CF364A)(Notes Note 5: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O. Note 6: The 16 grayscale test pattern tests device power ...
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FIGURE 6. DS90CF384A/DS90CF364A (Receiver) Clock In to Clock Out Delay FIGURE 7. DS90CF384A/DS90CF364A (Receiver) Phase Lock Loop Set Time FIGURE 8. 28 Parallel TTL Data Inputs Mapped to LVDS Outputs - DS90CF384A www.national.com 10087006 6 10087007 10087009 ...
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FIGURE 9. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs - DS90CF364A FIGURE 10. DS90CF384A/DS90CF364A (Receiver) Power Down Delay 10087008 7 10087010 www.national.com ...
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FIGURE 11. DS90CF384A (Receiver) LVDS Input Strobe Position www.national.com 8 10087025 ...
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FIGURE 12. DS90CF364A (Receiver) LVDS Input Strobe Position 9 10087026 www.national.com ...
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C—Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max Tppos—Transmitter output pulse position (min and max) RSKM = Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) + ISI ...
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DS90CF384A Pin Descriptions — 56L TSSOP Package — 24-Bit FPD Link Receiver Pin Name I/O No. RxIN Positive LVDS differentiaI data inputs. RxIN− Negative LVDS differential data inputs. RxOUT O 28 TTL level data outputs. This ...
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DS90CF384A Pin Summary — 64 ball FBGA Package — FPD Link Receiver Pin Name I/O No. RxIN Positive LVDS differentiaI data inputs. RxIN− Negative LVDS differential data inputs. RxOUT O 28 TTL level data outputs. This ...
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By Pin D3 RxOUT19 D4 RxOUT13 D5 RxOUT10 D6 VCC D7 RxOUT2 D8 GND E1 RxOUT22 E2 RxOUT24 E3 GND E4 LVDS VCC E5 LVDS GND E6 PWR DWN E7 RxCLKOUT E8 RxOUT0 F1 RxOUT23 F2 RxOUT26 ...
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Pin Diagram for TSSOP Packages DS90CF384A www.national.com 10087023 14 DS90CF364A 10087013 ...
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... Molded Thin Shrink Small Outline Package, JEDEC 48-Lead Molded Thin Shrink Small Outline Package, JEDEC Dimensions shown in millimeters only Order Number DS90CF384AMTD NS Package Number MTD56 Dimensions shown in millimeters only Order Number DS90CF364AMTD NS Package Number MTD48 15 www.national.com ...
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Fine Pitch Ball Grid Array (FBGA) Package www.national.com Dimensions shown in millimeters only Order Number DS90CF384ASLC NS Package Number SLC64A 16 ...
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Notes 17 www.national.com ...
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