DS90LV032ATM National Semiconductor, DS90LV032ATM Datasheet - Page 3

• Manufacturer Part Number: DS90LV032ATM
• Description: IC,LINE RECEIVER,QUAD,CMOS,DIFFERENTIAL,SOP,16PIN,PLASTIC
• Manufacturer: National Semiconductor

Specifications of DS90LV032ATM

• Rohs Compliant: NO

Symbol
t
t
t
t
f
PHZ
PLZ
PZH
PZL
MAX
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (Notes 3, 4, 7, 8)
Switching Characteristics
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground unless otherwise speci-
fied.
Note 3: All typicals are given for: V
Note 4: Generator waveform for all tests unless otherwise specified: f = 1 MHz, Z
Note 5: The VCMR range is reduced for larger VID. Example: if VID = 400mV, the VCMR is 0.2V to 2.2V. The fail-safe condition with inputs shorted is valid over
a common-mode range of 0V to 2.3V. A VID up to V
and Differential Pulse skew decrease when VID is increased from 200mV to 400mV. Skew specifications apply for 200mV
range .
Note 6: t
Note 7: t
any event on the inputs.
Note 8: t
and within 5˚C of each other within the operating temperature range.
Note 9: t
operating temperature and voltage ranges, and across process distribution. t
Note 10: ESD Rating:
Note 11: Output short circuit current (I
exceed maximum junction temperature specification.
Note 12: C
Note 13: V
AC specifications, the common voltage range is 0.1V to 2.3V
Note 14: f
V
Parameter Measurement Information
OL
HBM (1.5 k , 100 pF)
EIAJ (0 , 200 pF)
(max 0.4V), V
SKD1
SKD2
SKD3
SKD4
Disable Time High to Z
Disable Time Low to Z
Enable Time Z to High
Enable Time Z to Low
Maximum Operating Frequency (Note 14)
MAX
L
CC
includes probe and jig capacitance.
, Channel-to-Channel Skew, is defined as the difference between the propagation delay of one channel and that of the others on the same chip with
, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices at the same V
, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over recommended
is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel
generator input conditions: t
is always higher than R
OH
(min 2.7V), Load = 10 pF (stray plus probes)
250V
4.5kV
FIGURE 1. Receiver Propagation Delay and Transition Time Test Circuit
FIGURE 2. Receiver Propagation Delay and Transition Time Waveforms
CC
IN+
OS
= +3.3V, T
Parameter
) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, do not
and R
r
= t
f
<
IN−
1ns (0% to 100%), 50% duty cycle, differential (1.05V to 1.35V peak to peak). Output Criteria: 60%/40% duty cycle,
A
CC
voltage. R
= +25˚C.
− 0V may be applied to the R
(Continued)
IN−
and R
IN+
are allowed to have a voltage range −0.2V to V
SKD4
3
is defined as |Max − Min| differential propagation delay.
IN+
O
= 50 , t
/ R
IN−
R
C
( Figure 3 and Figure 4 )
All Channels Switching
L
L
inputs with the Common-Mode voltage set to V
= 2 k
= 10 pF
r
and t
Conditions
f
(0% to 100%)
DS100067-3
3 ns for R
CC
DS100067-4
− VID/2. However, to be compliant with
VID
Min
200
IN
.
800mV over the common-mode
Typ
250
11
11
8
6
CC
/2. Propagation delay
Max
www.national.com
12
12
17
17
Units
MHz
CC
ns
ns
ns
ns
,