DS92001TLD National Semiconductor, DS92001TLD Datasheet

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DS92001TLD

Manufacturer Part Number
DS92001TLD
Description
IC,Repeater Interface,LLCC,8PIN,PLASTIC
Manufacturer
National Semiconductor
Datasheet

Specifications of DS92001TLD

Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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© 2006 National Semiconductor Corporation
DS92001
3.3V B/LVDS-BLVDS Buffer
General Description
The DS92001 B/LVDS-BLVDS Buffer takes a BLVDS input
signal and provides an BLVDS output signal. In many large
systems, signals are distributed across backplanes, and one
of the limiting factors for system speed is the "stub length" or
the distance between the transmission line and the untermi-
nated receivers on individual cards. Although it is generally
recognized that this distance should be as short as possible
to maximize system performance, real-world packaging con-
cerns often make it difficult to make the stubs as short as the
designer would like.
The DS92001 has edge transitions optimized for multidrop
backplanes where the switching frequency is in the 200 MHz
range or less. The output edge rate is critical in some sys-
tems where long stubs may be present, and utilizing a slow
transition allows for longer stub lengths.
The DS92001, available in the LLP (Leadless Leadframe
Package) package, will allow the receiver inputs to be placed
very close to the main transmission line, thus improving
system performance.
A wide input dynamic range allows the DS92001 to receive
differential signals from LVPECL as well as LVDS sources.
This will allow the device to also fill the role of an LVPECL-
BLVDS translator.
Connection and Block Diagrams
SOIC - Top View
LLP - Top View
DS200247
20024705
20024743
The LOS pin detects a non-driven B/LVDS bus state at the
input and provides an active LOW output. The LOS pin can
be tied to the device’s output enable pin (EN) to generate a
TRI-STATE output state when the input is un-driven. The
LOS pin can also be used locally to inform the system of the
bus state.
Features
n Single +3.3 V Supply
n B/LVDS receiver inputs accept LVPECL signals
n TRI-STATE outputs
n Loss of Signal (LOS) pin detects a non-driven bus
n Receiver input threshold
n Fast propagation delay of 1.4 ns (typ)
n Low jitter 400 Mbps fully differential data path
n Compatible with BLVDS 10-bit SerDes (40MHz)
n Compatible with ANSI/TIA/EIA-644-A LVDS standard
n Available in SOIC and space saving LLP package
n Industrial Temperature Range
Functional Operation
Ordering Information
Order Number
DS92001TMA
DS92001TLD
OPEN/SHORTor Terminated
BLVDS Inputs
[IN+] − [IN−]
Full Fail-safe
VID ≤ −0.1V
VID ≥ 0.1V
NS Pkg. No.
M08A
LDA08A
<
±
100 mV
OUT+
BLVDS Outputs
H
H
L
September 2006
Pkg. Type
SOIC
LLP
20024702
www.national.com
OUT−
H
L
L

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DS92001TLD Summary of contents

Page 1

... Available in SOIC and space saving LLP package n Industrial Temperature Range Functional Operation 20024705 BLVDS Inputs [IN+] − [IN−] VID ≥ 0.1V VID ≤ −0.1V Full Fail-safe OPEN/SHORTor Terminated Ordering Information Order Number 20024743 DS92001TMA DS92001TLD DS200247 September 2006 < ± 100 mV 20024702 BLVDS Outputs OUT+ OUT− ...

Page 2

... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( LVCMOS/LVTTL Input Voltage (EN) LVCMOS/LVTTL Output Voltage (LOS) B/LVDS Receiver Input Voltage (IN+, IN−) BLVDS Driver Output Voltage (OUT+, OUT−) ...

Page 3

Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 2, 3) Symbol Parameter BLVDS OUTPUT DC SPECIFICATIONS (OUT) I Output Short Circuit Current OS1 (Note 4) I Differential Output Short Circuit OSD Current (Note 4) B/LVDS ...

Page 4

AC Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. (Note 3) Symbol Parameter LVDS OUTPUT AC SPECIFICATIONS (OUT) t Fall Time (Notes 5, 10) HLT 80% to 20% points t Disable Time (Active High to Z) ...

Page 5

DC Test Circuits FIGURE 2. Differential Driver Full Load DC Test Circuit AC Test Circuits and Timing Diagrams FIGURE 4. Propagation Delay Low-to-High and High-to-Low FIGURE 1. Differential Driver DC Test Circuit FIGURE 3. BLVDS Output Load 5 20024703 20024708 ...

Page 6

AC Test Circuits and Timing Diagrams FIGURE 7. Output active to TRI-STATE and TRI-STATE to active output time FIGURE 8. LOS Output Load for Propagation Delay, and Rise/Fall Times www.national.com (Continued) FIGURE 5. BLVDS Output Transition Time FIGURE 6. TRI-STATE ...

Page 7

AC Test Circuits and Timing Diagrams FIGURE 9. LOS Output Waveforms for Propagation Delay, and Rise/Fall Times DS92001 Pin Descriptions (SOIC and LLP) Pin Name Pin # Input/Output GND 1 IN − 2 IN+ 3 LOS ...

Page 8

Typical Applications www.national.com FIGURE 10. Backplane Stub-Hider Application FIGURE 11. Cable Repeater Application 8 20024711 20024710 ...

Page 9

Application Information The DS92001 can be used as a "stub-hider." In many sys- tems, signals are distributed across backplanes, and one of the limiting factors for system speed is the "stub length" or the distance between the transmission line and ...

Page 10

Application Information Avoid 90˚ turns (these cause impedance discontinuities). Use arcs or 45˚ bevels. Within a pair of traces, the distance between the two traces should be minimized to maintain common-mode rejection of the receivers. On the printed circuit board, ...

Page 11

... Physical Dimensions inches (millimeters) unless otherwise noted Order Number DS92001TMA See NS Package Number M08A Order Number DS92001TLD See NS Package Number LDA08A 11 www.national.com ...

Page 12

... BANNED SUBSTANCE COMPLIANCE National Semiconductor follows the provisions of the Product Stewardship Guide for Customers (CSP-9-111C2) and Banned Substances and Materials of Interest Specification (CSP-9-111S2) for regulatory environmental compliance. Details may be found at: www.national.com/quality/green. ...

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