DSPIC30F1010T-30I/SO Microchip Technology, DSPIC30F1010T-30I/SO Datasheet - Page 31

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DSPIC30F1010T-30I/SO

Manufacturer Part Number
DSPIC30F1010T-30I/SO
Description
6KB, Flash, 256bytes-RAM, 30MIPS, 21I/O, 16-bit Family,nanoWatt 28 SOIC .300in T
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr

Specifications of DSPIC30F1010T-30I/SO

Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
6KB (2K x 24)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Data Bus Width
16 bit
Data Ram Size
256 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
30 MHz
Number Of Programmable I/os
21
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240002, DM300023, DM330011
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM300023 - KIT DEMO DSPICDEM SMPS BUCK
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
DSPIC30F1010T-30I/SOTR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC30F1010T-30I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
3.0
3.1
The program address space is 4M instruction words. It
is addressable by a 24-bit value from either the 23-bit
PC, table instruction Effective Address (EA), or data
space EA, when program space is mapped into data
space, as defined by Table 3-1. Note that the program
space address is incremented by two between succes-
sive program words, in order to provide compatibility
with data space addressing.
User program space access is restricted to the lower
4M instruction word address range (0x000000 to
0x7FFFFE), for all accesses other than TBLRD/TBLWT,
which use TBLPAG<7> to determine user or configura-
tion space access. In Table 3-1, Read/Write instruc-
tions, bit 23 allows access to the Device ID, the User ID
and the Configuration bits. Otherwise, bit 23 is always
clear.
© 2006 Microchip Technology Inc.
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046). For more information on the device
instruction set and programming, refer to the “dsPIC30F/
33F Programmer’s Reference Manual” (DS70157).
Note:
MEMORY ORGANIZATION
Program Address Space
The address map shown in Figure 3-1 is
conceptual, and the actual memory con-
figuration may vary across individual
devices depending on available memory.
Preliminary
FIGURE 3-1:
dsPIC30F1010/202X
Reset –
Reset – Target Address
Alternate Vector Table
Arithmetic Warn. Trap
Device Configuration
Ext. Osc. Fail Trap
Address Error Trap
Stack Error Trap
Program Memory
(4K instructions)
UNITID (32 instr.)
PROGRAM SPACE MEMORY
MAP FOR dsPIC30F1010/
202X
Reserved
User Flash
DEVID (2)
GOTO
Reserved
Reserved
Reserved
(Read 0’s)
Vector 52
Vector 53
Reserved
Reserved
Registers
Vector 0
Vector 1
Reserved
Reserved
Instruction
DS70178C-page 29
000000
000002
000004
000014
00007E
000080
0000FE
000100
001FFE
002000
7FFFFE
800000
8005BE
8005C0
8005FE
800600
F7FFFE
F80000
F8000E
F80010
FEFFFE
FF0000
FFFFFE
Vector Tables

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