DSPIC30F2011T-20E/SO Microchip Technology, DSPIC30F2011T-20E/SO Datasheet - Page 90
![IC,DSP,16-BIT,CMOS,SOP,18PIN,PLASTIC](/photos/6/76/67656/150-18-soic_sml.jpg)
DSPIC30F2011T-20E/SO
Manufacturer Part Number
DSPIC30F2011T-20E/SO
Description
IC,DSP,16-BIT,CMOS,SOP,18PIN,PLASTIC
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2011-20ISO.pdf
(210 pages)
3.DSPIC30F2011-20ISO.pdf
(14 pages)
4.DSPIC30F2011-20ISO.pdf
(6 pages)
5.DSPIC30F2011-20ISO.pdf
(18 pages)
6.DSPIC30F2011-20IP.pdf
(26 pages)
Specifications of DSPIC30F2011T-20E/SO
Rohs Compliant
YES
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
12KB (4K x 24)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
18-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC30F005 - MODULE SCKT DSPIC30F 18DIP/SOIC
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- DSPIC30F2011-20ISO PDF datasheet
- DSPIC30F2011-20ISO PDF datasheet #2
- DSPIC30F2011-20ISO PDF datasheet #3
- DSPIC30F2011-20ISO PDF datasheet #4
- DSPIC30F2011-20ISO PDF datasheet #5
- DSPIC30F2011-20IP PDF datasheet #6
- Current page: 90 of 210
- Download datasheet (3Mb)
dsPIC30F2011/2012/3012/3013
12.5
When the CPU enters Sleep mode, all internal clocks
are stopped. Therefore, when the CPU enters the
Sleep state, the output compare channel drives the pin
to the active state that was observed prior to entering
the CPU Sleep state.
For example, if the pin was high when the CPU entered
the Sleep state, the pin remains high. Likewise, if the
pin was low when the CPU entered the Sleep state, the
pin remains low. In either case, the output compare
module resumes operation when the device wakes up.
12.6
When the CPU enters the Idle mode, the output
compare module can operate with full functionality.
The output compare channel operates during the CPU
Idle mode if the OCSIDL bit (OCxCON<13>) is at logic
‘0’ and the selected time base (Timer2 or Timer3) is
enabled and the TSIDL bit of the selected timer is set
to logic ‘0’.
DS70139G-page 90
Output Compare Operation During
CPU Sleep Mode
Output Compare Operation During
CPU Idle Mode
12.7
The output compare channels have the ability to
generate an interrupt on a compare match, for
whichever Match mode has been selected.
For all modes except the PWM mode, when a compare
event occurs, the respective interrupt flag (OCxIF) is
asserted and an interrupt is generated if enabled. The
OCxIF bit is located in the corresponding IFS register
and must be cleared in software. The interrupt is
enabled via the respective compare interrupt enable
(OCxIE) bit located in the corresponding IEC Control
register.
For the PWM mode, when an event occurs, the
respective timer interrupt flag (T2IF or T3IF) is asserted
and an interrupt is generated if enabled. The IF bit is
located in the IFS0 register and must be cleared in
software. The interrupt is enabled via the respective
timer interrupt enable bit (T2IE or T3IE) located in the
IEC0 Control register. The output compare interrupt
flag is never set during the PWM mode of operation.
Output Compare Interrupts
© 2010 Microchip Technology Inc.
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