DSPIC30F2011T-30I/SO Microchip Technology, DSPIC30F2011T-30I/SO Datasheet - Page 136
DSPIC30F2011T-30I/SO
Manufacturer Part Number
DSPIC30F2011T-30I/SO
Description
IC,DSP,16-BIT,CMOS,SOP,18PIN,PLASTIC
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2011-20ISO.pdf
(210 pages)
3.DSPIC30F2011-20ISO.pdf
(14 pages)
4.DSPIC30F2011-20ISO.pdf
(6 pages)
5.DSPIC30F2011-20ISO.pdf
(18 pages)
6.DSPIC30F2011-20IP.pdf
(26 pages)
Specifications of DSPIC30F2011T-30I/SO
Rohs Compliant
YES
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
12KB (4K x 24)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
18-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC30F005 - MODULE SCKT DSPIC30F 18DIP/SOIC
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- DSPIC30F2011-20ISO PDF datasheet
- DSPIC30F2011-20ISO PDF datasheet #2
- DSPIC30F2011-20ISO PDF datasheet #3
- DSPIC30F2011-20ISO PDF datasheet #4
- DSPIC30F2011-20ISO PDF datasheet #5
- DSPIC30F2011-20IP PDF datasheet #6
- Current page: 136 of 210
- Download datasheet (3Mb)
TABLE 17-7:
TABLE 17-8:
RCON
OSCCON
OSCTUN
PMD1
PMD2
Legend:
Note
FOSC
FWDT
FBORPOR F80004
FBS
FSS
FGS
FICD
Legend:
Note
Name
SFR
Name
1:
2:
3:
1:
2:
3:
Address
0740
0742
0744
0770
0772
Address
F80000
F80002
F80006
F80008
F8000A
F8000C
— = unimplemented bit, read as ‘0’
Reset state depends on type of reset.
Reset state depends on Configuration bits.
Only available on dsPIC30F3013 devices.
— = unimplemented bit, read as ‘0’
These bits are reserved (read as ‘1’ and must be programmed as ‘1’).
Reserved bits read as ‘1’ and must be programmed as ‘1’.
The FGS<2> bit is a read-only copy of the GCP bit (FGS<1>).
TRAPR
SYSTEM INTEGRATION REGISTER MAP
DEVICE CONFIGURATION REGISTER MAP
Bit 15
—
—
—
—
FWDTEN
MCLREN
BKBUG
Bit 15
FCKSM<1:0>
—
—
—
IOPUWR
Bit 14
—
—
—
Bit 14
COSC<2:0>
COE
—
—
—
—
—
Bit 13
BGST LVDEN
T3MD
—
—
Bit 13
—
—
—
—
—
Bit 12
T2MD
Reserved
Reserved
—
—
Bit 12
Bit 11
T1MD
(2)
(2)
—
—
—
—
—
—
—
—
Bit 10
—
—
—
LVDL<3:0>
Bit 11
—
—
—
—
—
—
—
NOSC<2:0>
IC2MD IC1MD
Bit 9
—
—
PWMPIN
Bit 10
—
—
—
—
—
Bit 8
—
—
(1)
FOS<2:0>
I2CMD U2MD
HPOL
EXTR
Bit 7
Bit 9
—
—
POST<1:0>
—
—
—
—
Reserved
(1)
SWR
Reserved
Bit 6
—
—
LPOL
Bit 8
(2)
(3)
—
—
—
(1)
SWDTEN
(2)
U1MD
LOCK
Bit 5
—
—
BOREN
Bit 7
—
—
—
—
—
—
WDTO
Bit 4
—
—
—
—
Bit 6
—
—
—
—
—
—
—
SPI1MD
SLEEP
TUN3
Bit 3
CF
—
Bit 5
—
FWPSA<1:0>
—
—
—
—
BORV<1:0>
TUN2
Bit 2
IDLE
—
—
—
Bit 4
LPOSCEN
—
—
—
—
OC2MD
TUN1
Bit 1
BOR
—
Bit 3
—
—
—
OSWEN
ADCMD
OC1MD
TUN0
Bit 0
POR
Reserved
FPR<4:0>
Bit 2
FWPSB<3:0>
—
—
Reserved
Reserved
0000 0000 0000 0000
0000 0000 0000 0000
(3)
Reset State
(Note 1)
(Note 2)
(Note 2)
(2)
(2)
Bit 1
GCP
FPWRT<1:0>
ICS<1:0>
GWRP
Bit 0
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