DSPIC30F2020-20E/MM Microchip Technology, DSPIC30F2020-20E/MM Datasheet - Page 18

• Manufacturer Part Number: DSPIC30F2020-20E/MM
• Description: 12KB, Flash, 512bytes-RAM, 30MIPS, 21I/O, 16-bit Family,nanoWatt 28 QFN-S 6x6mm
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2020-20E/MM

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-QFN
• Package: 28QFN-S EP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 21
• Interface Type: I2C/SPI/UART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300023 - KIT DEMO DSPICDEM SMPS BUCKAC164322 - MODULE SOCKET MPLAB PM3 28/44QFNDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

dsPIC30F Family Reference Manual
35.3.3.3
Figure 35-10: SPI Master, Frame Slave Connection Diagram
Figure 35-11: SPI Master, Frame Slave Timing (FRMDLY = 0)
Figure 35-12: SPI Master, Frame Slave Timing (FRMDLY = 1)
DS70272B-page 35-18
SPI Master, Frame Slave Mode
(FRMPOL = 1)
(FRMPOL = 0)
(FRMPOL = 1)
(FRMPOL = 0)
(SPI1 Master, Framed Slave)
(CKP = 1)
(CKP = 0)
(CKP = 1)
(CKP = 0)
Write to SPI1BUF
In the SPI Master/Frame Slave mode, the module generates the clock signal but uses the Slave
module frame synchronization signal for data transmission (Figure 35-10). This mode is enabled
by setting the MSTEN, FRMEN and SPIFSD bits to ‘1’.
In this mode, the SS1 pin is an input and is sampled on the sample edge of the SPI1 clock. When
it is sampled in its active state, data will be transmitted on the subsequent transmit edge of the
SPI1 clock. The interrupt flag, SPI1IF, is set when the transmission is complete. The user
application must make sure that the correct transmission data is loaded into the SPI1BUF before
the signal is received at the SS1 pin.
SDO1
SDO1
SCK1
SCK1
SCK1
SCK1
SDI1
SDI1
SS1
SS1
SS1
SS1
dsPIC30F
Write to SPI1BUF
SDO1
SCK1
SDI1
SS1
Sample SS1 pin for Pulse
Serial Clock
Frame Synchronization
Pulse
bit 15
bit 15
bit 15
bit 15
SDI1
SDO1
SCK1
SS1
bit 14
bit 14
bit 14
bit 14
Pulse Generated by SS1;
Receive Samples at SDI1
Receive Samples at SDI1
PROCESSOR 2
bit 13
bit 13
bit 13
bit 13
© 2008 Microchip Technology Inc.
bit 12
bit 12
bit 12
bit 12