DSPIC30F2020-20E/MM Microchip Technology, DSPIC30F2020-20E/MM Datasheet - Page 11

• Manufacturer Part Number: DSPIC30F2020-20E/MM
• Description: 12KB, Flash, 512bytes-RAM, 30MIPS, 21I/O, 16-bit Family,nanoWatt 28 QFN-S 6x6mm
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2020-20E/MM

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-QFN
• Package: 28QFN-S EP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 21
• Interface Type: I2C/SPI/UART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300023 - KIT DEMO DSPICDEM SMPS BUCKAC164322 - MODULE SOCKET MPLAB PM3 28/44QFNDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

18. Module: Output Compare
19. Module: Output Compare
© 2010 Microchip Technology Inc.
The output compare module will miss a compare
event when the current duty cycle register
(OCxRS) value is 0x0000 (0% duty cycle) and the
OCxRS register is updated with a value of 0x0001.
The compare event is missed only the first time a
value of 0x0001 is written to OCxRS and the PWM
output remains low for one PWM period.
Subsequent PWM high and low times occur as
expected.
Work around
None. If the current OCxRS register value is
0x0000, avoid writing a value of 0x0001 to
OCxRS. Instead, write a value of 0x0002;
however, in this case the duty cycle will be slightly
different from the desired value.
Affected Silicon Revisions
When the output compare module is operated in
the Dual Compare Match mode, a timer compare
match with the value in the OCxR register sets the
OCx output, producing a rising edge on the OCx
pin. Then, when a timer compare match with the
value in the OCxRS register occurs, the OCx
output is reset, producing a falling edge on the
OCx pin.
The above statement applies to all conditions
except when the difference between OCxR and
OCxRS is 1. In this case, the output compare
module may miss the Reset compare event and
cause the OCx pin to remain continuously high.
This condition will remain until the difference
between values in the OCxR and OCxRS registers
is made greater than 1.
Work around
Ensure in software that the difference between
values in OCxR and OCxRS registers is
maintained greater than 1.
Affected Silicon Revisions
A1
A1
X
X
A2
A2
X
X
A3
A3
X
X
20. Module: SPI
21. Module: SPI
Note:
Note:
dsPIC30F1010/202X
The SPI module slave select functionality
(enabled by setting SSEN = 1) will not function
correctly. Whether the SSx pin (x = 1 or 2) is high
or low, the SPI data transfer will be completed
and an interrupt will be generated. This applies
to the dsPIC30F2023 device only.
Work around
Manually poll the SSx pin state in the SPI interrupt
by reading the associated PORT bit:
• If the PORT bit is ‘0’, perform the required data
• If the PORT bit is ‘1’, clear the SPI interrupt flag
Affected Silicon Revisions
The SPI module will fail to generate frame syn-
chronization pulses when configured in the
Frame Master mode if the start of data is
selected to coincide with the start of the frame
synchronization
SPIFSD = 0). However, the module functions
correctly in Frame Slave mode, and also in
Frame Master mode if FRMDLY = 0. This
applies to the dsPIC30F2023 device only.
Work around
Manually drive the SSx pin (x = 1 or 2) high
using the associated PORT register, and then
drive it low after the required 1 bit-time pulse-
width. This operation needs to be performed
when the transmit buffer is written.
If FRMDLY = 0, no work around is needed.
Affected Silicon Revisions
A1
A1
read/write.
(SPIxIF), perform a dummy read of the
SPIx-BUF register, and return from the Interrupt
Service Routine.
X
X
The dsPIC30F1010/202X devices have
only one SPI. All references to x = 2 are
intended for software compatibility with
other dsPIC DSC devices.
The dsPIC30F1010/202X devices have
only one SPI. All references to x = 2 are
intended for software compatibility with
other dsPIC DSC devices.
A2
A2
X
X
A3
A3
X
X
pulse
DS80445D-page 11
(FRMEN = 1,