DSPIC30F2020T-30I/MM Microchip Technology, DSPIC30F2020T-30I/MM Datasheet - Page 151

• Manufacturer Part Number: DSPIC30F2020T-30I/MM
• Description: 12KB, Flash, 512bytes-RAM, 30MIPS, 21I/O, 16-bit Family,nanoWatt 28 QFN-S 6x6mm
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2020T-30I/MM

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300023 - KIT DEMO DSPICDEM SMPS BUCK
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F2020T-30I/MMTR

REGISTER 13-1:
© 2006 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12-7
bit 6
bit 5-2
bit 1
bit 0
SPIEN
R/W-0
U-0
—
SPIEN: SPIx Enable bit
1 = Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins
0 = Disables module
Unimplemented: Read as ‘0’
SPISIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
Unimplemented: Read as ‘0’
SPIROV: Receive Overflow Flag bit
1 = A new byte/word is completely received and discarded. The user software has not read the
0 = No overflow has occurred
Unimplemented: Read as ‘0’
SPITBF: SPIx Transmit Buffer Full Status bit
1 = Transmit not yet started, SPIxTXB is full
0 = Transmit started, SPIxTXB is empty
Automatically set in hardware when CPU writes SPIxBUF location, loading SPIxTXB.
Automatically cleared in hardware when SPIx module transfers data from SPIxTXB to SPIxSR.
SPIRBF: SPIx Receive Buffer Full Status bit
1 = Receive complete, SPIxRXB is full
0 = Receive is not complete, SPIxRXB is empty
Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB.
Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB.
SPIROV
R/C-0
previous data in the SPIxBUF register.
U-0
—
SPIxSTAT: SPIx STATUS AND CONTROL REGISTER
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
SPISIDL
R/W-0
U-0
—
U-0
U-0
Preliminary
—
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
U-0
—
—
dsPIC30F1010/202X
U-0
U-0
—
—
x = Bit is unknown
SPITBF
U-0
R-0
—
DS70178C-page 149
SPIRBF
U-0
R-0
—
bit 8
bit 0