DSPIC30F2023T-30I/ML Microchip Technology, DSPIC30F2023T-30I/ML Datasheet - Page 189
DSPIC30F2023T-30I/ML
Manufacturer Part Number
DSPIC30F2023T-30I/ML
Description
12KB, Flash, 512bytes-RAM, 30MIPS, 35I/O, 16-bit Family,nanoWatt 44 QFN 8x8x0.9m
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.AC164335.pdf
(286 pages)
2.DM300023.pdf
(22 pages)
3.DM300023.pdf
(18 pages)
4.DSPIC30F2011-20ISO.pdf
(66 pages)
5.DSPIC30F2011-20IP.pdf
(26 pages)
6.DSPIC30F1010-30ISO.pdf
(26 pages)
7.DSPIC30F1010-30ISO.pdf
(50 pages)
Specifications of DSPIC30F2023T-30I/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
12KB (4K x 24)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
DSPIC30F2023T-30I/MLTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC30F2023T-30I/ML
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- AC164335 PDF datasheet
- DM300023 PDF datasheet #2
- DM300023 PDF datasheet #3
- DSPIC30F2011-20ISO PDF datasheet #4
- DSPIC30F2011-20IP PDF datasheet #5
- DSPIC30F1010-30ISO PDF datasheet #6
- DSPIC30F1010-30ISO PDF datasheet #7
- Current page: 189 of 286
- Download datasheet (5Mb)
FIGURE 16-4:
© 2006 Microchip Technology Inc.
adc_clk
sample_even
sample_odd
sample_odd
connectx_en
connect_second
convert_en
capture_first_data
capture_second_data
state counter
Note 1: For all analog input pairs that do not have dedicated sample and hold circuits, the common sample and hold circuit
0
2: For all analog input pairs that have dedicated sample and hold circuits, the common sample and hold circuit samples
1
(1)
(2)
samples the input at the start of the first and second conversions. Therefore, the samples are sequential, not
simultaneous.
the input at the start of the first conversion so that both samples (odd and even) are near simultaneous.
10th 9th 8th
Dependent on S&H availability
2
connect_common
3
DETAILED CONVERSION SEQUENCE TIMINGS, SEQSAMP = 1
4
T
7th
AD
5
6th
6
5th
7
4th
8
3rd 2nd 1st
9
Preliminary
10
11
12
13
dsPIC30F1010/202X
10th 9th 8th
14
15
16
17
7th
18
6th
19
5th
20
4th
DS70178C-page 187
21
3rd 2nd 1st
22
23
0
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