DSPIC30F4012-20E/SO Microchip Technology, DSPIC30F4012-20E/SO Datasheet - Page 110
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
DSPIC30F4012-20E/SO
Manufacturer Part Number
DSPIC30F4012-20E/SO
Description
IC,DSP,16-BIT,CMOS,SOP,28PIN,PLASTIC
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F4012-30ISO.pdf
(238 pages)
3.DSPIC30F4012-30ISO.pdf
(18 pages)
4.DSPIC30F4012-30ISO.pdf
(6 pages)
5.DSPIC30F4012-30ISO.pdf
(16 pages)
6.DSPIC30F4012-30ISO.pdf
(22 pages)
Specifications of DSPIC30F4012-20E/SO
Rohs Compliant
YES
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
20
Program Memory Size
48KB (16K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
DSPIC30F401220ESO
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC30F4012-20E/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- DSPIC30F2011-20ISO PDF datasheet
- DSPIC30F4012-30ISO PDF datasheet #2
- DSPIC30F4012-30ISO PDF datasheet #3
- DSPIC30F4012-30ISO PDF datasheet #4
- DSPIC30F4012-30ISO PDF datasheet #5
- DSPIC30F4012-30ISO PDF datasheet #6
- Current page: 110 of 238
- Download datasheet (4Mb)
dsPIC30F4011/4012
16.2
The module supports a basic framed SPI protocol in
Master or Slave mode. The control bit, FRMEN,
enables framed SPI support and causes the SS1 pin to
perform the frame synchronization pulse (FSYNC)
function. The control bit, SPIFSD, determines whether
FIGURE 16-1:
FIGURE 16-2:
DS70135G-page 110
SDO1
SCK1
SDI1
Framed SPI Support
SS1
MSb
PROCESSOR 1
SPI BLOCK DIAGRAM
SPI MASTER/SLAVE CONNECTION
Serial Input Buffer
SPI Master
SS1 and
FSYNC
Shift Register
Control
Receive
(SPI1BUF)
(SPI1SR)
SPI1BUF
Read
bit 0
SPI1SR
LSb
Control
Clock
SDO1
SCK1
SDI1
Clock
Shift
SPI1BUF
Write
Transmit
Data Bus
Internal
Serial Clock
Select
Edge
the SS1 pin is an input or an output (i.e., whether the
module receives or generates the frame synchroniza-
tion pulse). The frame pulse is an active-high pulse for
a single SPI clock cycle. When frame synchronization
is enabled, the data transmission starts only on the
subsequent transmit edge of the SPI clock.
SDI1
SDO1
SCK1
Enable Master Clock
1, 2, 4, 6, 8
Secondary
Prescaler
MSb
Serial Input Buffer
Shift Register
PROCESSOR 2
(SPI1BUF)
(SPI1SR)
SPI Slave
© 2010 Microchip Technology Inc.
1, 4, 16, 64
Prescaler
Primary
LSb
F
CY
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