DSPIC30F4013-20E/P Microchip Technology, DSPIC30F4013-20E/P Datasheet - Page 132
![IC,DSP,16-BIT,CMOS,DIP,40PIN,PLASTIC](/photos/6/61/66192/150-40-dip_sml.jpg)
DSPIC30F4013-20E/P
Manufacturer Part Number
DSPIC30F4013-20E/P
Description
IC,DSP,16-BIT,CMOS,DIP,40PIN,PLASTIC
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2011-20IP.pdf
(26 pages)
3.DSPIC30F3014-30IPT.pdf
(228 pages)
4.DSPIC30F3014-30IPT.pdf
(16 pages)
5.DSPIC30F3014-30IPT.pdf
(6 pages)
6.DSPIC30F3014-30IPT.pdf
(14 pages)
7.DSPIC30F3014-30IPT.pdf
(20 pages)
Specifications of DSPIC30F4013-20E/P
Rohs Compliant
YES
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT
Number Of I /o
30
Program Memory Size
48KB (16K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 13x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
AC30F003 - MODULE SOCKET DSPIC30F 40DIPACICE0206 - ADAPTER MPLABICE 40P 600 MIL
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
DSPIC30F4013-20EP
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F4013-20E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
dsPIC30F3014/4013
19.1
The module contains a 16-word, dual port read-only
buffer, called ADCBUF0...ADCBUFF, to buffer the A/D
results. The RAM is 12 bits wide but the data obtained
is represented in one of four different 16-bit data for-
mats. The contents of the sixteen A/D Conversion
Result Buffer registers, ADCBUF0 through ADCBUFF,
cannot be written by user software.
19.2
After the A/D module has been configured, the sample
acquisition is started by setting the SAMP bit. Various
sources, such as a programmable bit, timer time-outs
and external events, terminate acquisition and start a
conversion. When the A/D conversion is complete, the
result is loaded into ADCBUF0...ADCBUFF, and the
DONE bit and the A/D Interrupt Flag, ADIF, are set after
the number of samples specified by the SMPI bit. The
ADC module can be configured for different interrupt
rates as described in
Conversion
The following steps should be followed for doing an
A/D conversion:
1.
2.
3.
4.
5.
6.
7.
DS70138G-page 132
Configure the A/D module:
• Configure analog pins, voltage reference and
• Select A/D input channels
• Select A/D conversion clock
• Select A/D conversion trigger
• Turn on A/D module
Configure A/D interrupt (if required):
• Clear ADIF bit
• Select A/D interrupt priority
• Set ADIE bit (for ISR processing)
Start sampling
Wait the required acquisition time
Trigger acquisition end, start conversion:
Wait for A/D conversion to complete, by either:
• Waiting for the A/D interrupt, or
• Waiting for the DONE bit to get set.
Read A/D result buffer, clear ADIF if required
digital I/O
A/D Result Buffer
Conversion Operation
Sequence”.
Section 19.3 “Selecting the
19.3
Several groups of control bits select the sequence in
which the A/D connects inputs to the sample/hold
channel, converts a channel, writes the buffer memory
and generates interrupts.
The sequence is controlled by the sampling clocks.
The SMPI bits select the number of acquisition/
conversion sequences that would be performed before
an interrupt occurs. This can vary from 1 sample per
interrupt to 16 samples per interrupt.
The BUFM bit splits the 16-word results buffer into two
8-word groups. Writing to the 8-word buffers is
alternated on each interrupt event.
Use of the BUFM bit depends on how much time is
available for moving the buffers after the interrupt.
If the processor can quickly unload a full buffer within
the time it takes to acquire and convert one channel,
the BUFM bit can be ‘0’ and up to 16 conversions (cor-
responding to the 16 input channels) may be done per
interrupt. The processor has one acquisition and
conversion time to move the sixteen conversions.
If the processor cannot unload the buffer within the
acquisition and conversion time, the BUFM bit should be
‘1’. For example, if SMPI<3:0> (ADCON2<5:2>) = 0111,
then eight conversions are loaded into 1/2 of the buffer,
following which an interrupt occurs. The next eight con-
versions are loaded into the other 1/2 of the buffer. The
processor has the entire time between interrupts to
move the eight conversions.
The ALTS bit can be used to alternate the inputs
selected during the sampling sequence. The input
multiplexer has two sets of sample inputs: MUX A and
MUX B. If the ALTS bit is ‘0’, only the MUX A inputs are
selected for sampling. If the ALTS bit is ‘1’ and
SMPI<3:0> = 0000 on the first sample/convert
sequence, the MUX A inputs are selected and on the
next acquire/convert sequence, the MUX B inputs are
selected.
The CSCNA bit (ADCON2<10>) allows the S/H input to
be sequentially scanned across a selected number of
analog inputs for the MUX A group. The inputs are
selected by the ADCSSL register. If a particular bit in
the ADCSSL register is ‘1’, the corresponding input is
selected. The inputs are always scanned from lower to
higher numbered inputs, starting after each interrupt. If
the number of inputs selected is greater than the
number of samples taken per interrupt, the higher
numbered inputs are unused.
Note:
Selecting the Conversion Sequence
The ADCHS, ADPCFG and ADCSSL reg-
isters allow the application to configure
AN13-AN15 as analog input pins. Since
these pins are not physically present on
the device, conversion results from these
pins read ‘0’.
2010 Microchip Technology Inc.