DSPIC30F5011-20E/PT Microchip Technology, DSPIC30F5011-20E/PT Datasheet - Page 132
DSPIC30F5011-20E/PT
Manufacturer Part Number
DSPIC30F5011-20E/PT
Description
IC,DSP,16-BIT,CMOS,TQFP,64PIN,PLASTIC
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2011-20IP.pdf
(26 pages)
3.DSPIC30F5011-20IPT.pdf
(220 pages)
4.DSPIC30F5011-20IPT.pdf
(16 pages)
5.DSPIC30F5011-20IPT.pdf
(6 pages)
6.DSPIC30F5011-20IPT.pdf
(14 pages)
7.DSPIC30F5011-20IPT.pdf
(26 pages)
Specifications of DSPIC30F5011-20E/PT
Rohs Compliant
YES
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
Number Of I /o
52
Program Memory Size
66KB (22K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
64-TFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC30F008 - MODULE SKT FOR DSPIC30F 64TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DSPIC30F5011-20E/PTG
DSPIC30F501120EPT
DSPIC30F501120EPT
DSPIC30F501120EPT
DSPIC30F501120EPT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F5011-20E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- DSPIC30F2011-20ISO PDF datasheet
- DSPIC30F2011-20IP PDF datasheet #2
- DSPIC30F5011-20IPT PDF datasheet #3
- DSPIC30F5011-20IPT PDF datasheet #4
- DSPIC30F5011-20IPT PDF datasheet #5
- DSPIC30F5011-20IPT PDF datasheet #6
- DSPIC30F5011-20IPT PDF datasheet #7
- Current page: 132 of 220
- Download datasheet (4Mb)
dsPIC30F5011/5013
FIGURE 19-3:
19.8
The analog input model of the 12-bit ADC is shown in
Figure
function of the internal amplifier settling time and the
holding capacitor charge time.
For the ADC to meet its specified accuracy, the charge
holding capacitor (C
charge to the voltage level on the analog input pin. The
source impedance (R
(R
FIGURE 19-4:
DS70116J-page 132
IC
Instruction Execution BSET ADCON1, ASAM
), and the internal sampling switch (R
ADCBUF0
ADCBUF1
19-4. The total sampling time for the ADC is a
ADCLK
ADC Acquisition Requirements
DONE
SAMP
Note: C
Legend: C
VA
PIN
HOLD
Rs
S
value depends on device package and is not tested. Effect of C
CONVERTING 1 CHANNEL AT 200 KSPS, AUTO-SAMPLE START, 1 T
SAMPLING TIME
12-BIT ADC ANALOG INPUT MODEL
), the interconnect impedance
V
I leakage
R
R
C
ANx
) must be allowed to fully
PIN
T
IC
SS
HOLD
C
PIN
= 1 T
T
SAMP
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch resistance
= sample/hold capacitance (from DAC)
AD
various junctions
V
SS
DD
V
V
) imped-
T
T
= 0.6V
= 0.6V
= 14 T
T
CONV
AD
R
I leakage
± 500 nA
= 1 T
T
IC
SAMP
≤ 250Ω
AD
ance combine to directly affect the time required to
charge the capacitor C
of the analog sources must therefore be small enough
to fully charge the holding capacitor within the chosen
sample time. To minimize the effects of pin leakage cur-
rents on the accuracy of the ADC, the maximum rec-
ommended source impedance, R
analog input channel is selected (changed), this sam-
pling function must be completed prior to starting the
conversion. The internal holding capacitor will be in a
discharged state prior to each sample operation.
Sampling
Switch
R
SS
= 14 T
PIN
T
CONV
R
negligible if Rs ≤ 2.5 kΩ.
SS
V
AD
SS
C
= DAC capacitance
= 18 pF
≤ 3 kΩ
HOLD
HOLD
© 2011 Microchip Technology Inc.
. The combined impedance
S
, is 2.5 kΩ. After the
AD
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