DSPIC30F6014A-20E/PF Microchip Technology, DSPIC30F6014A-20E/PF Datasheet - Page 39
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DSPIC30F6014A-20E/PF
Manufacturer Part Number
DSPIC30F6014A-20E/PF
Description
Digital Signal Processor
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2011-20IP.pdf
(26 pages)
3.DSPIC30F6011A-30IPT.pdf
(234 pages)
4.DSPIC30F6011A-30IPT.pdf
(8 pages)
5.DSPIC30F6011A-30IPT.pdf
(10 pages)
6.DSPIC30F6011A-30IPT.pdf
(6 pages)
7.DSPIC30F6011A-30IPT.pdf
(8 pages)
8.DSPIC30F6011A-30IPT.pdf
(16 pages)
Specifications of DSPIC30F6014A-20E/PF
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
144KB (48K x 24)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
80-TQFP, 80-VQFP
Package
80TQFP
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
20 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16 Bit
Number Of Programmable I/os
68
Interface Type
CAN/I2C/SPI/UART
On-chip Adc
16-chx12-bit
Number Of Timers
5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM300024 - KIT DEMO DSPICDEM 1.1DM300019 - BOARD DEMO DSPICDEM 80L STARTERDM300004-2 - BOARD DEMO DSPICDEM.NET 2DM300004-1 - BOARD DEMO DSPICDEM.NET 1AC164314 - MODULE SKT FOR PM3 80PFAC30F001 - MODULE SOCKET DSPIC30F 80TQFPXLT80PT2 - SOCKET TRANSITION ICE 80TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F6014A-20E/PF
Manufacturer:
MICROCHIP
Quantity:
12 000
Company:
Part Number:
DSPIC30F6014A-20E/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
DSPIC30F6014A-20E/PF
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
4.0
The dsPIC DSC core contains two independent
address generator units: the X AGU and Y AGU. The Y
AGU supports word sized data reads for the DSP MAC
class of instructions only. The dsPIC30F AGUs
support:
• Linear Addressing
• Modulo (Circular) Addressing
• Bit-Reversed Addressing
Linear and Modulo Data Addressing modes can be
applied to data space or program space. Bit-Reversed
Addressing is only applicable to data space addresses.
4.1
The Addressing modes in
the Addressing modes optimized to support the specific
features of individual instructions. The Addressing
modes provided in the MAC class of instructions are
somewhat different from those in the other instruction
types.
TABLE 4-1:
© 2011 Microchip Technology Inc.
File Register Direct
Register Direct
Register Indirect
Register Indirect Post-modified
Register Indirect Pre-modified
Register Indirect with Register Offset The sum of Wn and Wb forms the EA.
Register Indirect with Literal Offset
Note:
ADDRESS GENERATOR UNITS
Instruction Addressing Modes
Addressing Mode
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC
Programmer’s
(DS70157).
FUNDAMENTAL ADDRESSING MODES SUPPORTED
dsPIC30F6011A/6012A/6013A/6014A
Table 4-1
Reference
form the basis of
The address of the File register is specified explicitly.
The contents of a register are accessed directly.
The contents of Wn forms the EA.
The contents of Wn forms the EA. Wn is post-modified (incremented or
decremented) by a constant value.
Wn is pre-modified (incremented or decremented) by a signed constant value
to form the EA.
The sum of Wn and a literal forms the EA.
Manual”
4.1.1
Most File register instructions use a 13-bit address field
(f) to directly address data present in the first 8192
bytes of data memory (Near data space). Most File
register instructions employ a working register, W0,
which is denoted as WREG in these instructions. The
destination is typically either the same File register or
WREG (with the exception of the MUL instruction),
which writes the result to a register or register pair. The
MOV instruction allows additional flexibility and can
access the entire data space.
4.1.2
The three-operand MCU instructions are of the form:
Operand 3 = Operand 1 <function> Operand 2
where:
Operand
Addressing mode can only be Register Direct) which is
referred to as Wb.
Operand 2 can be a W register, fetched from data
memory or a 5-bit literal. The result location can be
either a W register or a data memory location. The fol-
lowing addressing modes are supported by MCU
instructions:
• Register Direct
• Register Indirect
• Register Indirect Post-modified
• Register Indirect Pre-modified
• 5-bit or 10-bit Literal
Note:
Description
FILE REGISTER INSTRUCTIONS
MCU INSTRUCTIONS
Not all instructions support all the
addressing modes given above. Individual
instructions may support different subsets
of these addressing modes.
1 is always a working register (i.e., the
DS70143E-page 39