DSPIC30F6014AT-20E/PT Microchip Technology, DSPIC30F6014AT-20E/PT Datasheet - Page 135
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DSPIC30F6014AT-20E/PT
Manufacturer Part Number
DSPIC30F6014AT-20E/PT
Description
Digital Signal Processor
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2011-20IP.pdf
(26 pages)
3.DSPIC30F6011A-30IPT.pdf
(234 pages)
4.DSPIC30F6011A-30IPT.pdf
(8 pages)
5.DSPIC30F6011A-30IPT.pdf
(10 pages)
6.DSPIC30F6011A-30IPT.pdf
(6 pages)
7.DSPIC30F6011A-30IPT.pdf
(8 pages)
8.DSPIC30F6011A-30IPT.pdf
(16 pages)
Specifications of DSPIC30F6014AT-20E/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
144KB (48K x 24)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
80-TFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM300024 - KIT DEMO DSPICDEM 1.1XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPDM300004-2 - BOARD DEMO DSPICDEM.NET 2DM300004-1 - BOARD DEMO DSPICDEM.NET 1AC30F007 - MODULE SKT FOR DSPIC30F 80TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F6014AT-20E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
DSPIC30F6014AT-20E/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
19.4
The conversion trigger will terminate acquisition and
start the requested conversions.
The SSRC<2:0> bits select the source of the
conversion trigger. The SSRC bits provide for up to four
alternate sources of conversion trigger.
When SSRC<2:0> = 000, the conversion trigger is
under software control. Clearing the SAMP bit will
cause the conversion trigger event after ~11 T
When SSRC<2:0> = 111 (Auto-Start mode), the con-
version trigger is under ADC clock control. The SAMC
bits select the number of ADC clocks between the start
of acquisition and the start of conversion. This provides
the fastest conversion rates on multiple channels.
SAMC must always be at least one clock cycle.
Other trigger sources can come from timer modules or
external interrupts.
19.5
Clearing the ADON bit during a conversion will abort
the current conversion and stop the sampling sequenc-
ing until the next sampling trigger. The ADCBUF will not
be updated with the partially completed ADC conver-
sion sample. That is, the ADCBUF will continue to con-
tain the value of the last completed conversion (or the
last value written to the ADCBUF register).
If the clearing of the ADON bit coincides with an auto-
start, the clearing has a higher priority and a new
conversion will not start.
19.6
The ADC conversion requires 14 T
the ADC conversion clock is software selected, using a
6-bit counter. There are 64 possible options for T
EQUATION 19-1:
© 2011 Microchip Technology Inc.
Programming the Start of
Conversion Trigger
Aborting a Conversion
Selecting the ADC Conversion
Clock
T
AD
= T
CY
* (0.5*(ADCS<5:0> + 1))
CLOCK
dsPIC30F6011A/6012A/6013A/6014A
ADC CONVERSION
AD
. The source of
AD
.
AD
.
The internal RC oscillator is selected by setting the
ADRC bit.
For correct ADC conversions, the ADC conversion
clock (T
time of 334 nsec (for V
“Electrical Characteristics”
other operating conditions.
Example 19-1
ADCS<5:0> bits, assuming a device operating speed
of 30 MIPS.
EXAMPLE 19-1:
Since,
Sampling Time = Acquisition Time + Conversion Time
Therefore,
Sampling Rate =
If SSRC<2:0> = ‘111’ and SAMC<4:0> = ‘00001’
Therefore,
Set ADCS<5:0> = 19
AD
ADCS<5:0> = 2
Minimum T
) must be selected to ensure a minimum T
Actual T
shows a sample calculation for the
= ~200 kHz
= 1 T
= 15 x 334 nsec
AD
T
(15 x 334 nsec)
AD
CY
AD
=
= 2 •
= 19.04
=
= 334 nsec
DD
ADC CONVERSION
CLOCK AND SAMPLING
RATE CALCULATION
= 334 nsec
= 33 .33 nsec (30 MIPS)
+ 14 T
T
33.33 nsec
= 5V). Refer to
1
T
T
CY
2
AD
CY
33.33 nsec
334 nsec
2
AD
for minimum T
(ADCS<5:0> + 1)
– 1
DS70143E-page 135
(19 + 1)
– 1
Section 23.0
AD
under
AD