ENC28J60T/SS Microchip Technology, ENC28J60T/SS Datasheet - Page 6

• Manufacturer Part Number: ENC28J60T/SS
• Description: 8 KB RAM, MAC&PHY, Ethernet Controller 28 SSOP .209in T/R
• Manufacturer: Microchip Technology

Specifications of ENC28J60T/SS

• Controller Type: Ethernet Controller, MAC/10Base-T
• Interface: SPI
• Voltage - Supply: 3.1 V ~ 3.6 V
• Current - Supply: 160mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM163024 - BOARD DEMO PICDEM.NET 2AC164123 - BOARD DAUGHTER ETH PICTAIL PLUSAC164121 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ENC28J60
EXAMPLE 1:
14. Module: Memory (Ethernet Buffer)
EXAMPLE 2:
DS80349C-page 6
if (Next Packet Pointer = ERXST)
ERXRDPT = ERXND
ERXRDPT = Next Packet Pointer – 1
then:
else:
The receive hardware may corrupt the circular
receive buffer (including the Next Packet Pointer
and receive status vector fields) when an even value
is programmed into the ERXRDPTH:ERXRDPTL
registers.
Work around
Ensure that only odd addresses are written to the
ERXRDPT registers. Assuming that ERXND con-
tains an odd value, many applications can derive a
suitable value to write to ERXRDPT by subtracting
one from the Next Packet Pointer (a value always
ensured to be even because of hardware padding)
and then compensating for a potential ERXST to
ERXND wrap-around. Assuming that the receive
buffer area does not span the 1FFFh to 0000h mem-
ory boundary, the logic in Example 2 will ensure that
ERXRDPT is programmed with an odd value:
Affected Silicon Revisions
B1
X
ECON1.TXRST
ECON1.TXRST
EIR.TXERIF
EIR.TXIF
ECON1.TXRTS
while(EIR.TXIF = 0 and EIR.TXERIF = 0)
ECON1.TXRTS
read tsv
for retrycount = 0 to 15
next retrycount
if (EIR.TXERIF and tsv<Transmit Late Collision>) then
else
end if
B4
X
NOP
ECON1.TXRST
ECON1.TXRST
EIR.TXERIF
EIR.TXIF
ECON1.TXRTS
while(EIR.TXIF = 0 and EIR.TXERIF = 0)
ECON1.TXRTS
read tsv
exit for
B5
X
= 1
= 0
= 0
= 0
= 1
B7
X
= 0
NOP
= 1
= 0
= 0
= 0
= 1
= 0
15. Module: Transmit Logic
If a collision occurs after 64 bytes have been
transmitted, the transmit logic may not set the Late
Collision Error status bit (ESTAT.LATECOL).
Work around
Whenever a late collision has potentially occurred
(both EIR.TXERIF and ESTAT.TXABRT bits will be
set), read the transmit status vector and check the
transmit late collision bit (bit 29).
Affected Silicon Revisions
B1
X
B4
X
B5
X
 2010 Microchip Technology Inc.
B7
X