LM2641MTC-ADJ National Semiconductor, LM2641MTC-ADJ Datasheet - Page 14

• Manufacturer Part Number: LM2641MTC-ADJ
• Description: Power Supply IC
• Manufacturer: National Semiconductor

Specifications of LM2641MTC-ADJ

• Power Dissipation Pd: 883mW
• No. Of Pins: 28
• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

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Application Information
Looking at the plot, it can be seen that the unity-gain cross-
over frequency f
value, the phase margin at the point is calculated to be about
84˚.
To verify the accuracy of these calculations, the circuit was
bench tested using a network analyzer. The measured gain
and phase are shown plotted in Figure 7 .
The measured gain plot agrees very closely to the predicted
values. The phase margin at 0dB is slightly less than pre-
dicted (71˚ vs. 84˚), which is to be expected due to the nega-
tive phase shift contributions of high frequency poles not in-
cluded in this simplified analysis.
It should be noted that 70˚ phase margin with 25kHz band-
width is excellent, and represents the optimal compensation
for this set of values for V
Optimizing Stability
The best tool for measuring both bandwidth and phase mar-
gin is a network analyzer. If this is not available, a simple
method which gives a good measure of loop stability is to ap-
ply a minimum to maximum step of output load current and
observe the resulting output voltage transient. A design
FIGURE 6. Calculated Gain Plot for 3.3V/4A Application
FIGURE 7. Measured Gain/Phase Plot for 3.3V/4A
c
is expected to be about 25kHz. Using this
Application
IN
, V
OUT
, inductor and R
(Continued)
DS100949-7
DS100949-8
L
.
14
which has good phase margin (
ringing after the output voltage transient returns to its nomi-
nal value.
It should be noted that the stability (phase margin) does not
have to be optimal for the regulator to be stable. The design
analyzed in the previous section was re-compensated by
changing R11 and C10 to intentionally reduce the phase
margin to about 35˚ and re-tested for step response. The
output waveform displayed slight ringing after the initial re-
turn to nominal, but was completely stable otherwise.
In most cases, the compensation components shown in the
Typical Application Circuits will give good performance. To
assist in optimizing phase margin, the following guidelines
show the effects of changing various components.
C
quency of the pole f
loop bandwidth. Increasing C
ing the phase margin) if the loop bandwidth is too wide
(
to the unity-gain crossover frequency.
ESR of C
needed to cancel negative phase shift near the unity-gain
frequency. High-ESR capacitors can not be used, since the
zero will be too low in frequency which will make the loop
bandwidth too wide.
R11/C10: These form a pole and a zero. Changing the value
of C10 changes the frequency of both the pole and zero.
Note that since this causes the frequency of both the pole
and zero to move up or down together, adjusting the value of
C10 does not significantly affect loop bandwidth.
Changing the value of R11 moves the frequency location of
the zero f
(since the value of R11 is much less than the 160k
impedance of the Gm amplifier). Since only the zero is
moved, this affects both bandwidth and phase margin. This
means adjusting R11 is an easy way to maximize the posi-
tive phase shift provided by the zero. Best results are typi-
cally obtained if f
(where f
Design Procedure
This section presents guidelines for selecting external com-
ponents.
INDUCTOR SELECTION
In selecting an inductor, the parameters which are most im-
portant are inductance, current rating, and DC resistance.
Inductance
It is important to understand that all inductors are not created
equal, as the method of specifying inductance varies widely.
It must also be noted that the inductance of every inductor
decreases with current. The core material, size, and con-
struction type all contribute the the inductor’s dependence
on current loading. Some inductors exhibit inductance
curves which are relatively flat, while others may vary more
than 2:1 from minimum to maximum current. In the latter
case, the manufacturer’s specified inductance value is usu-
ally the maximum value, which means the actual inductance
in your application will be much less.
An inductor with a flatter inductance curve is preferable,
since the loop characteristics of any switching converter are
affected somewhat by inductance value. An inductor which
has a more constant inductance value will give more consis-
tent loop bandwidth when the load current is varied.
>
OUT
F
OSC
: Increasing the capacitance of C
/5) which places the high-frequency poles too close
c
z
is the unity-gain crossover frequency).
(R11), but does not significantly shift the C10 pole
OUT
: The ESR forms a zero f
z
(R11) is in the frequency range of f
p
(C
OUT
) to a lower value and reduces
OUT
>
can be beneficial (increas-
50˚) will typically show no
OUT
z
(ESR), which is
moves the fre-
c
/4 to f
output
c