LM5115MTC National Semiconductor, LM5115MTC Datasheet - Page 10

• Manufacturer Part Number: LM5115MTC
• Description: IC,SMPS CONTROLLER,VOLTAGE-MODE,TSSOP,16PIN,PLASTIC
• Manufacturer: National Semiconductor

Specifications of LM5115MTC

• Rohs Compliant: NO

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Detailed Operating Description
The LM5115A controller contains all of the features neces-
sary to implement multiple output power converters utilizing
the Secondary Side Post Regulation (SSPR) technique. The
SSPR technique develops a highly efficient and well regulat-
ed auxiliary output from the secondary side switching wave-
form of an isolated power converter. Regulation of the
auxiliary output voltage is achieved by leading edge pulse
width modulation (PWM) of the main channel duty cycle.
Leading edge modulation is compatible with either current
mode or voltage mode control of the main output. The
LM5115A drives external high-side and low-side NMOS pow-
er switches configured as a synchronous buck regulator. A
current sense amplifier provides overload protection and op-
erates over a wide common mode input range from 0V to
13.5V. Additional features include a low dropout (LDO) bias
regulator, error amplifier, precision reference, adaptive dead
time control of the gate driver signals and thermal shutdown.
Low Drop-Out Bias Regulator (VCC)
The LM5115A contains an internal LDO regulator that oper-
ates over an input supply range from 4.5V to 30V. The output
of the regulator at the VCC pin is nominally regulated at 7V
and is internally current limited to 40mA. VCC is the main
supply to the internal logic, PWM controller, and gate driver
circuits. When power is applied to the VBIAS pin, the regulator
is enabled and sources current into an external capacitor
connected to the VCC pin. The recommended output capac-
itor range for the VCC regulator is 0.1uF to 100uF. When the
voltage at the VCC pin reaches the VCC under-voltage lock-
out threshold of 4.25V, the controller is enabled. The con-
troller is disabled if VCC falls below 4.0V (250mV hysteresis).
In applications where an appropriate regulated dc bias supply
is available, the LM5115A controller can be powered directly
through the VCC pin instead of the VBIAS pin. In this config-
uration, it is recommended that the VCC and the VBIAS pins
be connected together such that the external bias voltage is
applied to both pins. The allowable VCC range when biased
from an external supply is 4.5V to 7V.
FIGURE 2. Line Feed-Forward Diagram
10
Synchronization (SYNC) and Feed-
Forward (RAMP)
The pulsing “phase signal” from the main converter synchro-
nizes the PWM ramp and gate drive outputs of the LM5115A.
The phase signal is the square wave output from the trans-
former secondary winding before rectification (Figure 1). A
resistor connected from the phase signal to the low
impedance SYNC pin produces a square wave current
(I
SYNC input monitors I
ence. When I
(CLK) is reset and the capacitor connected to the RAMP be-
gins to charge. The current source that charges the RAMP
capacitor is equal to 3 times the I
of the phase signal sets the CLK signal and discharges the
RAMP capacitor until the next rising edge of the phase signal.
The RAMP capacitor is discharged to ground by a low
impedance
impedance at SYNC pin is 2.5kΩ which is normally much
smaller than the external SYNC pin resistance.
The RAMP and SYNC functions illustrated in Figure 2 provide
line voltage feed-forward to improve the regulation of the aux-
iliary output when the input voltage of the main converter
changes. Varying the input voltage to the main converter pro-
duces proportional variations in amplitude of the phase signal.
The main channel PWM controller adjusts the pulse width of
the phase signal to maintain constant volt*seconds and a
regulated main output as shown in Figure 3. The variation of
the phase signal amplitude and duration are reflected in the
slope and duty cycle of the RAMP signal of the LM5115A
(I
of the LM5115A is automatically adjusted to regulate the aux-
iliary output voltage with virtually no change in the PWM
threshold voltage. Transient line regulation is improved be-
cause the PWM duty cycle of the auxiliary converter is imme-
diately corrected, independent of the delays of the voltage
regulation loop.
SYNC
SYNC
) as shown in Figure 2. A current comparator at the
α phase signal amplitude). As a result, the duty cycle
(100Ω)
SYNC
exceeds 15µA, the internal clock signal
20207112
SYNC
n-channel
relative to an internal 15µA refer-
SYNC
MOSFET.
current. The falling edge
The
input