LM629N-6 National Semiconductor, LM629N-6 Datasheet - Page 12
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LM629N-6
Manufacturer Part Number
LM629N-6
Description
IC,Motor Controller,MOS,DIP,28PIN
Manufacturer
National Semiconductor
Datasheet
1.LM629N-6.pdf
(26 pages)
Specifications of LM629N-6
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SBPR
MSKI
RSTI
LFIL
UDF
LTRJ
STT
RDSTAT
RDSIGS
RDIP
RDDP
RDRP
RDDV
RDRV
RDSUM
Theory of Operation
Note 4: Commands may be executed “On the Fly” during motion.
Note 5: Commands not applicable to execution during motion.
Note 6: Command may be executed during motion if acceleration parameter was not changed.
Note 7: Command needs no code because the command port status-byte read is totally supported by hardware.
User Command Set
GENERAL
The following paragraphs describe the user command set of
the LM628. Some of the commands can be issued alone and
some require a supporting data structure. As examples, the
command STT (STarT motion) does not require additional
data; command LFIL (Load FILter parameters) requires ad-
ditional data (derivative-term sampling interval and/or filter
parameters).
Commands are categorized by function: initialization, inter-
rupt control, filter control, trajectory control, and data report-
ing. The commands are listed in Table 2 and described in the
following paragraphs. Along with each command name is its
command-byte code, the number of accompanying data
bytes that are to be written (or read), and a comment as to
whether the command is executable during motion.
Initialization Commands
The following four LM628 user commands are used primarily
to initialize the system for use.
RESET COMMAND: RESET THE LM628
This command (and the hardware reset input, Pin 27) results
in setting the following data items to zero: filter coefficients
and their input buffers, trajectory parameters and their input
buffers, and the motor control output. A zero motor control
output is a half-scale, offset-binary code: (80 hex for the 8-bit
output mode; 800 hex for 12-bit mode). During reset, the
DAC port outputs 800 hex to “zero” a 12-bit DAC and reverts
to 80 hex to “zero” an 8-bit DAC. The command also clears
Command
Command Code:
Data Bytes:
Executable During Motion: Yes
Interrupt
Interrupt
Interrupt
Filter
Filter
Trajectory
Trajectory
Report
Report
Report
Report
Report
Report
Report
Report
Type
00 Hex
None
(Continued)
TABLE 2. LM628 User Command Set (Continued)
Set Breakpoint, Relative
Mask Interrupts
Reset Interrupts
Load Filter Parameters
Update Filter
Load Trajectory
Start Motion
Read Status Byte
Read Signals Register
Read Index Position
Read Desired Position
Read Real Position
Read Desired Velocity
Read Real Velocity
Read Integration Sum
Description
12
five of the six interrupt masks (only the SBPA/SBPR interrupt
is masked), sets the output port size to 8 bits, and defines
the current absolute position as home. Reset, which may be
executed at any time, will be completed in less than 1.5 ms.
Also see commands PORT8 and PORT12.
PORT8 COMMAND: SET OUTPUT PORT SIZE TO 8
BITS
The default output port size of the LM628 is 8 bits; so the
PORT8 command need not be executed when using an 8-bit
DAC. This command must not be executed when using a
12-bit converter; it will result in erratic, unpredictable motor
behavior. The 8-bit output port size is the required selection
when using the LM629, the PWM-output version of the
LM628.
PORT12 COMMAND: SET OUTPUT PORT SIZE TO 12
BITS
When a 12-bit DAC is used, command PORT12 should be
issued very early in the initialization process. Because use of
this command is determined by system hardware, there is
only one foreseen reason to execute it later: if the RESET
command is issued (because an 8-bit output would then be
selected as the default) command PORT12 should be im-
mediately executed. This command must not be issued
when using an 8-bit converter or the LM629, the PWM-
output version of the LM628.
Command Code:
Data Bytes:
Executable During Motion: Not Applicable
Command Code:
Data Bytes:
Executable During Motion: Not Applicable
None
Hex
1C
1D
0C
0D
1E
1F
0A
0B
21
04
01
09
08
07
05 Hex
None
06 Hex
None
2 to 10
2 to 14
Bytes
Data
4
2
2
0
0
1
2
4
4
4
4
2
2
Note
1, 4
1
1
1
1
1
1
3
1
1
1
1
1
1
1