PIC16C717-I/SS Microchip Technology, PIC16C717-I/SS Datasheet - Page 101
![IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SSOP,20PIN,PLASTIC](/photos/6/58/65895/150-20-ssop_sml.jpg)
PIC16C717-I/SS
Manufacturer Part Number
PIC16C717-I/SS
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SSOP,20PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16F818-ISO.pdf
(6 pages)
2.PIC16C770-ISO.pdf
(220 pages)
3.PIC16C770-ISO.pdf
(6 pages)
4.PIC16C770-ISO.pdf
(8 pages)
Specifications of PIC16C717-I/SS
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
OTP
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
309-1016 - ADAPTER 20-SSOP TO 18-DIP
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PIC16C717I/SS
- PIC16F818-ISO PDF datasheet
- PIC16C770-ISO PDF datasheet #2
- PIC16C770-ISO PDF datasheet #3
- PIC16C770-ISO PDF datasheet #4
- Current page: 101 of 220
- Download datasheet (4Mb)
9.2.18
For Standard mode I
resistors R
lowing parameters
• Supply voltage
• Bus capacitance
• Number of connected devices (input current +
The supply voltage limits the minimum value of resistor
R
at V
FIGURE 9-31:
TABLE 9-3:
Legend:
p
10Bh,18Bh
2002 Microchip Technology Inc.
leakage current).
Note: I
0Bh, 8Bh,
Address
due to the specified minimum sink current of 3 mA
OL
0Ch
8Ch
0Dh
8Dh
13h
14h
91h
94h
93h
max = 0.4V for the specified output stages. For
connected.
2
C devices with input levels related to V
x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the MSSP in I
p
CONNECTION CONSIDERATIONS
FOR I
and R
SSPCON2
SSPSTAT
SSPCON
SSPBUF
SSPADD
INTCON
Name
PIR1
PIE1
PIR2
PIE2
REGISTERS ASSOCIATED WITH I
2
s
C BUS
in Figure 9-31 depends on the fol-
2
SAMPLE DEVICE CONFIGURATION FOR I
C bus devices, the values of
WCOL
LVDIE
GCEN
LVDIF
Bit 7
SMP
GIE
—
—
SDA
SCL
ACKSTAT
SSPOV
PEIE
ADIF
ADIE
Bit 6
CKE
—
—
Synchronous Serial Port Receive Buffer/Transmit Register
Rp
Synchronous Serial Port (I
SSPEN
ACKDT
DD
Bit 5
T0IE
Advance Information
D/A
—
—
—
—
Rp
must have one common supply line to which the pull-up resistor is also
ACKEN
Bit 4
INTE
CKP
—
—
—
—
P
Rs
V
2
DD
2
DEVICE
SSPM3
C Mode) Address Register
C OPERATION
SSPIF
SSPIE
BCLIE
BCLIF
RCEN
RBIE
Bit 3
Rs
+ 10%
S
example, with a supply voltage of V
V
1.7 k
The desired noise margin of 0.1V
limits the maximum value of R
optional and used to improve ESD susceptibility.
The bus capacitance is the total capacitance of wire,
connections, and pins. This capacitance limits the max-
imum value of R
(Figure 9-31).
The SMP bit is the slew rate control enabled bit. This bit
is in the SSPSTAT register, and controls the slew rate
of the I/O pins when in I
OL
PIC16C717/770/771
CCP1IE
max = 0.4V at 3 mA, R
CCP1IF
SSPM2
Bit 2
T0IF
PEN
R/W
—
—
V
2
DD
C BUS
as a function of R
TMR2IF
TMR2IE
SSPM1
RSEN
INTF
Bit 1
UA
—
—
p
due to the specified rise time
TMR1IE
TMR1IF
CCP2IF
CCP2IE
SSPM0
2
RBIF
Bit 0
C mode (master or slave).
SEN
BF
Cb=10 pF to 400 pF
2
p
p min
C mode.
is shown in Figure 9-31.
s
0000 000x
-0-- 0000
-0-- 0000
0--- 0--0
0--- 0--0
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
POR, BOR
. Series resistors are
DD
= (5.5-0.4)/0.003 =
DD
DS41120B-page 99
for the low level
= 5V+10% and
MCLR, WDT
0000 000u
-0-- 0000
-0-- 0000
0--- 0--0
0--- 0--0
uuuu uuuu
0000 0000
0000 0000
0000 0000
0000 0000
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