PIC16C773/SS Microchip Technology, PIC16C773/SS Datasheet - Page 87

• Manufacturer Part Number: PIC16C773/SS
• Description: 28 PIN, 7KB OTP, 256 RAM, 22 I/O,
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C773/SS

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 309-1025 - ADAPTER 28-SSOP TO 28-DIP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.2.14
A stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit PEN (SSPCON2<2>). At the end of a receive/trans-
mit the SCL line is held low after the falling edge of the
ninth clock. When the PEN bit is set, the master will
assert the SDA line low . When the SDA line is sam-
pled low, the baud rate generator is reloaded and
counts down to 0. When the baud rate generator times
out, the SCL pin will be brought high, and one T
(baud rate generator rollover count) later, the SDA pin
will be de-asserted. When the SDA pin is sampled high
FIGURE 8-31: STOP CONDITION RECEIVE OR TRANSMIT MODE
1999 Microchip Technology Inc.
STOP CONDITION TIMING
SCL
SDA
Write to SSPCON2
Falling edge of
9th clock
Note: T
ACK
Set PEN
BRG
= one baud rate generator period.
SDA asserted low before rising edge of clock
to setup stop condition.
T
T
BRG
BRG
Advance Information
BRG
T
SCL brought high after T
BRG
SCL = 1 for T
after SDA sampled high. P bit (SSPSTAT<4>) is set
P
T
BRG
while SCL is high, the P bit (SSPSTAT<4>) is set. A
T
set
Whenever the firmware decides to take control of the
bus, it will first determine if the bus is busy by checking
the S and P bits in the SSPSTAT register. If the bus is
busy, then the CPU can be interrupted (notified) when
a Stop bit is detected (i.e. bus is free).
8.2.14.14 WCOL STATUS FLAG
If the user writes the SSPBUF when a STOP sequence
is in progress, then WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
BRG
(Figure
BRG
PEN bit (SSPCON2<2>) is cleared by
later the PEN bit is cleared and the SSPIF bit is
hardware and the SSPIF bit is set
, followed by SDA = 1 for T
BRG
8-31).
PIC16C77X
BRG
DS30275A-page 87