PIC16F630-I/ML Microchip Technology, PIC16F630-I/ML Datasheet - Page 75
![1.75KB Flash, 64 RAM, 12 I/O 16 QFN 4x4mm TUBE](/photos/6/65/66536/mfg_mcp7386x_qfn_sml.jpg)
PIC16F630-I/ML
Manufacturer Part Number
PIC16F630-I/ML
Description
1.75KB Flash, 64 RAM, 12 I/O 16 QFN 4x4mm TUBE
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC12F629T-ISN.pdf
(24 pages)
3.PIC16F630-ISL.pdf
(132 pages)
4.PIC16F630-ISL.pdf
(2 pages)
5.PIC16F630-ISL.pdf
(10 pages)
Specifications of PIC16F630-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
12
Program Memory Size
1.75KB (1K x 14)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
16-QFN
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
64 B
Interface Type
RS- 232, USB
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFN
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
Details
10.2
ADDLW
Syntax:
Operands:
Operation:
Status Affected:
Description:
ADDWF
Syntax:
Operands:
Operation:
Status Affected:
Description:
ANDLW
Syntax:
Operands:
Operation:
Status Affected:
Description:
ANDWF
Syntax:
Operands:
Operation:
Status Affected:
Description:
2010 Microchip Technology Inc.
Instruction Descriptions
Add W and f
[label] ADDWF
0 f 127
d
(W) + (f) (destination)
C, DC, Z
Add the contents of the W register
with register ‘f’. If ‘d’ is 0, the
result is stored in the W register. If
‘d’ is 1, the result is stored back in
register ‘f’.
AND W with f
[label] ANDWF
0 f 127
d
(W) .AND. (f) (destination)
Z
AND the W register with register
‘f’. If ‘d’ is 0, the result is stored in
the W register. If ‘d’ is 1, the result
is stored back in register ‘f’.
[label] ADDLW
0 k 255
(W) + k (W)
C, DC, Z
The contents of the W register
are added to the eight-bit literal ‘k’
and the result is placed in the W
register.
[label] ANDLW
0 k 255
(W) .AND. (k) (W)
Z
The contents of W register are
AND’ed with the eight-bit literal
‘k’. The result is placed in the W
register.
Add Literal and W
AND Literal with W
k
f,d
k
f,d
BCF
Syntax:
Operands:
Operation:
Status Affected:
Description:
BSF
Syntax:
Operands:
Operation:
Status Affected:
Description:
BTFSS
Syntax:
Operands:
Operation:
Status Affected:
Description:
BTFSC
Syntax:
Operands:
Operation:
Status Affected:
Description:
PIC16F630/676
[label] BTFSS f,b
0 f 127
0 b < 7
skip if (f<b>) = 1
None
If bit ‘b’ in register ‘f’ is ‘0’, the next
instruction is executed.
If bit ‘b’ is ‘1’, then the next instruc-
tion is discarded and a NOP is
executed instead, making this a
2-cycle instruction.
Bit Test, Skip if Clear
[label] BTFSC f,b
0 f 127
0 b 7
skip if (f<b>) = 0
None
If bit ‘b’ in register ‘f’ is ‘1’, the next
instruction is executed.
If bit ‘b’, in register ‘f’, is ‘0’, the
next instruction is discarded, and
a NOP is executed instead, making
this a 2-cycle instruction.
Bit Test f, Skip if Set
Bit Clear f
[label] BCF
0 f 127
0 b 7
0 (f<b>)
None
Bit ‘b’ in register ‘f’ is cleared.
Bit Set f
[label] BSF
0 f 127
0 b 7
1 (f<b>)
None
Bit ‘b’ in register ‘f’ is set.
f,b
f,b
DS40039F-page 75