PIC16F676-E/SL Microchip Technology, PIC16F676-E/SL Datasheet - Page 16

• Manufacturer Part Number: PIC16F676-E/SL
• Description: 14 PIN, 1.75KB STD FLASH, 64 RAM, 12 I/O,
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F676-E/SL

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 12
• Program Memory Size: 1.75KB (1K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 64 B
• Interface Type: RS- 232, USB
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -
• Lead Free Status / Rohs Status: Details

PIC16F630/676
2.2.2.4
The PIE1 register contains the interrupt enable bits, as
shown in Register 2-4.
REGISTER 2-4:
DS40039F-page 16
bit 7
bit 6
bit 5-4
bit 3
bit 2-1
bit 0
PIE1 Register
PIE1 — PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS: 8Ch)
bit 7
EEIE: EE Write Complete Interrupt Enable bit
1 = Enables the EE write complete interrupt
0 = Disables the EE write complete interrupt
ADIE: A/D Converter Interrupt Enable bit (PIC16F676 only)
1 = Enables the A/D converter interrupt
0 = Disables the A/D converter interrupt
Unimplemented: Read as ‘0’
CMIE: Comparator Interrupt Enable bit
1 = Enables the comparator interrupt
0 = Disables the comparator interrupt
Unimplemented: Read as ‘0’
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Legend:
R = Readable bit
- n = Value at POR
R/W-0
EEIE
R/W-0
ADIE
U-0
—
W = Writable bit
‘1’ = Bit is set
U-0
—
Note:
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
CMIE
Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
U-0
—
 2010 Microchip Technology Inc.
x = Bit is unknown
U-0
—
TMR1IE
R/W-0
bit 0