PIC16F677T-I/ML Microchip Technology, PIC16F677T-I/ML Datasheet - Page 178
![IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,20PIN,PLASTIC](/photos/6/64/66481/c04-126_ml_sml.jpg)
PIC16F677T-I/ML
Manufacturer Part Number
PIC16F677T-I/ML
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,20PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F690DM-PCTLHS.pdf
(306 pages)
3.PIC16F677-IP.pdf
(2 pages)
4.PIC16F677-IP.pdf
(16 pages)
Specifications of PIC16F677T-I/ML
Rohs Compliant
YES
Mfg Application Notes
Intro to Capacitive Sensing Appl Notes Layout and Physical Design Appl Note
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
18
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
SSP
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
17
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNAC162061 - HEADER INTRFC MPLAB ICD2 20PINDVA1004 - DEVICE ADAPTER 8/14/20DIP
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F677T-I/ML
Manufacturer:
MCHP
Quantity:
4 776
Part Number:
PIC16F677T-I/ML035
Manufacturer:
MICRO
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC16F690DM-PCTLHS PDF datasheet #2
- PIC16F677-IP PDF datasheet #3
- PIC16F677-IP PDF datasheet #4
- Current page: 178 of 306
- Download datasheet (6Mb)
PIC16F631/677/685/687/689/690
12.4.2.3
The operation of the Synchronous Master and Slave
modes is identical (Section 12.4.1.5 “Synchronous
Master Reception”), with the following exceptions:
• Sleep
• CREN bit is always set, therefore the receiver is
• SREN bit, which is a “don't care” in Slave mode
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the
word is received, the RSR register will transfer the data
to the RCREG register. If the RCIE enable bit is set, the
interrupt generated will wake the device from Sleep
and execute the next instruction. If the GIE bit is also
set, the program will branch to the interrupt vector.
TABLE 12-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
DS41262E-page 176
BAUDCTL ABDOVF
INTCON
PIE1
PIR1
RCREG
RCSTA
SPBRG
SPBRGH
TRISB
TXREG
TXSTA
Legend:
never Idle
Name
x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave Reception.
EUSART Receive Data Register
EUSART Transmit Data Register
TRISB7
BRG15
SPEN
BRG7
CSRC
EUSART Synchronous Slave
Reception
Bit 7
GIE
—
—
TRISB6
BRG14
RCIDL
BRG6
PEIE
ADIE
ADIF
Bit 6
RX9
TX9
TRISB5
BRG13
SREN
BRG5
TXEN
RCIE
RCIF
Bit 5
T0IE
—
TRISB4
BRG12
CREN
SYNC
SCKP
BRG4
INTE
Bit 4
TXIE
TXIF
ADDEN
SENDB
BRG16
BRG11
RABIE
SSPIE
SSPIF
BRG3
Bit 3
CCP1IE
CCP1IF
BRG10
FERR
BRGH
BRG2
12.4.2.4
1.
2.
3.
4.
5.
6.
7.
8.
Bit 2
T0IF
—
Set the SYNC and SPEN bits and clear the
CSRC bit.
If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
If 9-bit reception is desired, set the RX9 bit.
Set the CREN bit to enable reception.
The RCIF bit will be set when reception is
complete. An interrupt will be generated if the
RCIE bit was set.
If 9-bit mode is enabled, retrieve the Most
Significant bit from the RX9D bit of the RCSTA
register.
Retrieve the 8 Least Significant bits from the
receive FIFO by reading the RCREG register.
If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register or by clearing the SPEN bit which resets
the EUSART.
TMR2IE
TMR2IF
OERR
TRMT
BRG1
BRG9
WUE
Bit 1
INTF
Synchronous Slave Reception
Set-up:
TMR1IE
TMR1IF
ABDEN
RABIF
RX9D
BRG0
BRG8
TX9D
Bit 0
© 2008 Microchip Technology Inc.
01-0 0-00
0000 000x
-000 0000
-000 0000
0000 0000
0000 000x
0000 0000
0000 0000
1111 ----
0000 0000
0000 0010
POR, BOR
Value on
01-0 0-00
0000 000x
-000 0000
-000 0000
0000 0000
0000 000x
0000 0000
0000 0000
1111 ----
0000 0000
0000 0010
Value on
all other
Resets
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