PIC16F677T-I/SS Microchip Technology, PIC16F677T-I/SS Datasheet - Page 96
![IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SSOP,20PIN,PLASTIC](/photos/6/58/65895/150-20-ssop_sml.jpg)
PIC16F677T-I/SS
Manufacturer Part Number
PIC16F677T-I/SS
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SSOP,20PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F690DM-PCTLHS.pdf
(306 pages)
3.PIC16F677-IP.pdf
(2 pages)
4.PIC16F677-IP.pdf
(16 pages)
Specifications of PIC16F677T-I/SS
Rohs Compliant
YES
Mfg Application Notes
Intro to Capacitive Sensing Appl Notes Layout and Physical Design Appl Note
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
18
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SSOP
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
SSP
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
18
Number Of Timers
2
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT20SS1-1 - SOCKET TRANSITION 20DIP 20SSOPDM164125 - BOARD DEMO PICDEM TOUCH SENSE 1AC162061 - HEADER INTRFC MPLAB ICD2 20PIN
Lead Free Status / Rohs Status
Details
- PIC16F616T-ISL PDF datasheet
- PIC16F690DM-PCTLHS PDF datasheet #2
- PIC16F677-IP PDF datasheet #3
- PIC16F677-IP PDF datasheet #4
- Current page: 96 of 306
- Download datasheet (6Mb)
PIC16F631/677/685/687/689/690
FIGURE 8-2:
FIGURE 8-3:
DS41262E-page 94
FixedRef
CV
C2V
FixedRef
CV
C1V
REF
REF
REN
REN
C12IN0-
C12IN1-
C12IN2-
C12IN3-
C12IN0-
C12IN1-
C12IN2-
C12IN3-
C2CH<1:0>
C2IN+
C1IN+
0
1
C1CH<1:0>
MUX
0
1
MUX
COMPARATOR C1 SIMPLIFIED BLOCK DIAGRAM
COMPARATOR C2 SIMPLIFIED BLOCK DIAGRAM
C2R
C1R
0
1
2
3
0
1
2
MUX
MUX
0
1
2
3
0
1
Note 1:
2
MUX
MUX
Note 1:
2:
3:
2:
3:
C2V
C2V
When C1ON = 0, the C1 comparator will produce a ‘0’ output to the XOR Gate.
Q1 and Q3 are phases of the four-phase system clock (F
Q1 is held high during Sleep mode.
C1V
C1V
When C2ON = 0, the C2 comparator will produce a ‘0’ output to the XOR Gate.
Q1 and Q3 are phases of the four-phase system clock (F
Q1 is held high during Sleep mode.
IN
IN
-
+
IN
IN
-
+
C2
C2ON
+
-
C1
C1ON
C2POL
(1)
C1POL
(1)
From TMR1
Q3*RD_CM2CON0
Clock
Q3*RD_CM1CON0
Q1
Q1
D
NRESET
C2OUT
D
EN
NRESET
D
EN
C1OUT
Q
Q
C2SYNC
Q
D
EN
C2POL
D
EN
CL
C1POL
0
1
MUX
CL
Q
Q
© 2008 Microchip Technology Inc.
to Timer1 Gate, SR latch
and other peripherals
To other peripherals
C1OUT (to SR latch)
OSC
RD_CM2CON0
OSC
RD_CM1CON0
).
).
SYNCC2OUT
Data Bus
Set C2IF
Data Bus
Set C1IF
To
To
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