PIC16F677T-I/SS Microchip Technology, PIC16F677T-I/SS Datasheet - Page 6

• Manufacturer Part Number: PIC16F677T-I/SS
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SSOP,20PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F677T-I/SS

• Rohs Compliant: YES
• Mfg Application Notes: Intro to Capacitive Sensing Appl Notes Layout and Physical Design Appl Note
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 18
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SSOP
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: SSP
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 2
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT20SS1-1 - SOCKET TRANSITION 20DIP 20SSOPDM164125 - BOARD DEMO PICDEM TOUCH SENSE 1AC162061 - HEADER INTRFC MPLAB ICD2 20PIN
• Lead Free Status / Rohs Status: Details

PIC16F631/677/685/687/689/690
2. Module: SSP (PIC16F687/689/690 only)
2.1 SSP module does not recognize first Start bit
EXAMPLE 1:
DS80243M-page 6
MOVLW
MOVWF
MOVLW
MOVWF
received.
In any of the I
to recognize the first Start bit received after a
transition from module disable to module enable.
Subsequent Stop bits and Start bits are detected
properly.
Work around
Enable the SSP module in SSPMSK Access mode
before changing the mode to the desired I
operation.
Fix
Rev. A6 Silicon and later revisions.
Affected Silicon Revisions
PIC16F677
PIC16F687/PIC16F689/PIC16F690
A1
A3
X
B’00111001’
SSPCON
B’00110110’
SSPCON
A4
X
2
A5
C™ modes, the SSP module will fail
X
CODE EXAMPLE
A6
;Module enable, clock
;enable, SSPMSK access.
;Optionally load
;address mask value
;into SSPMSK register.
;Module enable, clock
;enable, 7-bit address
;I
2
C slave.
2
C
2.2 Under certain conditions, the SSPIF flag sets
on reception of the first byte.
• On reception of the first byte modify the SSPM
Fix
None.
Affected Silicon Revisions
PIC16F677
PIC16F687/PIC16F689/PIC16F690
Work around
When all of the following conditions are met:
• The module is configured as a SPI slave
• CKP = 1
• CKE = 1
• Multiple bytes are sent with the SS line
The SSPIF flag will only be set on reception of the
first byte and the following bytes will not be
correctly received.
• Toggle the SS line between bytes
or
A1
A3
X
X
bits in the SSPCON register to configure the
module as a SPI slave with SS pin disabled.
Then restore the SSPM bits to the configuration
for SPI slave with SS pin enabled. The module
is then ready for reception of the following byte.
remaining low between bytes
A4
X
A5
X
 2010 Microchip Technology Inc.
A6
X