PIC16F73-E/SP Microchip Technology, PIC16F73-E/SP Datasheet - Page 119
PIC16F73-E/SP
Manufacturer Part Number
PIC16F73-E/SP
Description
28 PIN, 7KB STD FLASH, 192 RAM, 22 I/O,
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F818-ISO.pdf
(6 pages)
4.PIC16F73-ISP.pdf
(174 pages)
5.PIC16F73-ISP.pdf
(14 pages)
6.PIC16F73-ISP.pdf
(12 pages)
Specifications of PIC16F73-E/SP
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
28-DIP (0.300", 7.62mm)
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
192 B
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
22
Number Of Timers
3 bit
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000, DM163022
Minimum Operating Temperature
- 40 C
On-chip Adc
5 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
PIC16F73E/SP
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F818-ISO PDF datasheet #3
- PIC16F73-ISP PDF datasheet #4
- PIC16F73-ISP PDF datasheet #5
- PIC16F73-ISP PDF datasheet #6
- Current page: 119 of 688
- Download datasheet (3Mb)
7.8
7.9
7.10
1997 Microchip Technology Inc.
Protection Against Spurious Writes
Data EEPROM Operation During Code Protected Configuration
Initialization
There are conditions when the device may not want to write to the data EEPROM memory. To
protect against spurious EEPROM writes, various mechanisms have been built-in. On power-up,
WREN is cleared. Also, the Power-up Timer (72 ms duration) prevents EEPROM write.
The write initiate sequence and the WREN bit together help prevent an accidental write during
brown-outs, power glitches, and software malfunction.
When the device is code protected, the CPU is able to read and write data to the Data EEPROM.
For ROM devices, there are two code protection bits. One for the ROM program memory and one
for the Data EEPROM memory. See the Device Programming Specification for more information
about these bits.
The Data EEPROM module does not have an initialization sequence such as other modules. To
do a read of the Data EEPROM refer to
to
As for the General Purpose RAM, it is a good idea to initialize all Data EEPROM locations to a
known state. This initialization may take place at the time of device programming or an applica-
tion diagnostic mode, since on reset you may not want the Data EEPROM to be cleared.
An Application Diagnostic mode may be a condition on the I/O pins that the device tests for after
the device power-ups. Then depending on this mode, the device would do some diagnostic func-
tion. The state for the I/O pins would need to be something that would not be possible without the
injected levels to force this diagnostic mode.
Example
7-2, and to verify that the write completed successfully refer to
Section 7. Data EEPROM
Example
7-1. To do a write to the Data EEPROM refer
Example
DS31007A-page 7-7
7-3.
7
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