PIC16F767-E/ML Microchip Technology, PIC16F767-E/ML Datasheet - Page 61
PIC16F767-E/ML
Manufacturer Part Number
PIC16F767-E/ML
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,28PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F737-ISP.pdf
(276 pages)
4.PIC16F737-ISP.pdf
(10 pages)
Specifications of PIC16F767-E/ML
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
14KB (8K x 14)
Program Memory Type
FLASH
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F737-ISP PDF datasheet #3
- PIC16F737-ISP PDF datasheet #4
- Current page: 61 of 276
- Download datasheet (6Mb)
FIGURE 5-11:
2004 Microchip Technology Inc.
Note 1: Pin location of CCP2 is determined by the CCPMX bit in Configuration Word Register 1.
CCP2 Output Select and CCPMX
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
3: The SDA Schmitt Trigger conforms to the I
BLOCK DIAGRAM OF RB3/CCP2
RBPU
Data Bus
WR PORTB
WR TRISB
To A/D Channel Input
To CCP Module Input
(2)
CCP2 Output
RD PORTB
RD TRISB
TRIS Latch
Data Latch
D
D
CK
CK
Q
Q
Q
Schmitt Trigger
Buffer
(3)
Input Mode
Analog
2
(1)
C™ specification.
1
0
/AN9 PIN
Input Mode
Analog
Input Mode
Analog
Input Buffer
Q
TTL
EN
RD PORTB
D
PIC16F7X7
V
P
V
N
DD
SS
V
P
DD
Weak
Pull-up
I/O pin
DS30498C-page 59
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