PIC16F767-E/SS Microchip Technology, PIC16F767-E/SS Datasheet - Page 273

• Manufacturer Part Number: PIC16F767-E/SS
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SSOP,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F767-E/SS

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SSOP
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 368 B
• Interface Type: AUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• A/d Bit Size: 10 bit
• A/d Channels Available: 11
• Height: 1.75 mm
• Length: 10.2 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4 V
• Width: 5.3 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

16.5
16.5.1
1997 Microchip Technology Inc.
SSP Module / Basic SSP Module Compatibility
Initialization
Example 16-2: SPI Master Mode Initialization
When changing from the SSP Module to the Basic SSP module, the SSPSTAT register contains
two additional control bits. These bits are:
• SMP, SPI data input sample phase
• CKE, SPI Clock Edge Select
To be compatible with the SPI of the Basic SSP module, these bits must be appropriately config-
ured. If these bits are not at the states shown in
be expected. If the SSP module uses a different configuration then shown in
Basic SSP module can not be used to implement that mode. That mode may be implemented in
software.
Table 16-4: New Bit States for Compatibility
Basic SSP Module
CLRF
CLRF
MOVLW
MOVWF
BSF
BSF
BCF
BSF
MOVLW
MOVWF
CKP
1
0
STATUS
SSPSTAT
0x31
SSPCON
STATUS, RP0
PIE1, SSPIE
STATUS, RP0
INTCON, GIE
DataByte
SSPBUF
CKP
; Bank 0
; Clear status bits
; Set up SPI port, Master mode, CLK/16,
;
;
; Bank 1
; Bank 0
; Enable, enabled interrupts
; Data to be Transmitted
;
; Start Transmission
; Enable SSP interrupt
1
0
Data xmit on rising edge
Data sampled in middle
Could move data from RAM location
SSP Module
CKE
0
0
Table
Section 16. BSSP
16-4, improper SPI communication should
SMP
0
0
DS31016A-page 16-23
Table
16-4, the
16